Added Multiple Digital Verilog IPs

clkgatectrl/README.md

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+# clkgatectrl
+
+## Description
+
+This IP implements a Clock Gating Controller in Verilog.
+
+The controller generates gated clocks based on enable signals. A test mode is included to bypass clock gating and directly pass the clock for testing purposes.
+
+## Inputs
+
+* clk : Input clock
+* rst_n : Active-low reset
+* enable[3:0] : Enable signals for clock gating
+* test_mode : Test mode enable
+
+## Outputs
+
+* gated_clk[3:0] : Gated clock outputs
+
+## Files Included
+
+* Verilog source file
+* eSim test circuit project files
+
+## Author
+
+Yamini

clkgatectrl/Verilog Files/Clock_gating_controller_ip.v

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+
+
+module Clock_gating_controller_ip(
+    input  wire                  clk,
+    input  wire                  rst_n,
+    input  wire [3:0]   enable,
+    input  wire                  test_mode,
+
+    output wire [3:0]   gated_clk
+);
+
+    reg [3:0] enable_reg;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n)
+            enable_reg <= 0;
+        else
+            enable_reg <= enable;
+    end
+
+    // Clock gating
+    genvar j;
+    generate
+        for (j = 0; j <4; j = j + 1) begin : GATING
+            assign gated_clk[j] = test_mode ? clk : (clk & enable_reg[j]);
+        end
+    endgenerate
+
+endmodule

clkgatectrl/eSim Test Circuit Project Files/Clock_Gating_Controller-cache.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# clock_gating_controller_ip
+#
+DEF clock_gating_controller_ip U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "clock_gating_controller_ip" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 1100 0 1 0 N
+X clk0 1 2150 1900 200 R 50 50 1 1 I
+X rst_n0 2 2150 1800 200 R 50 50 1 1 I
+X enable3 3 2150 1700 200 R 50 50 1 1 I
+X enable2 4 2150 1600 200 R 50 50 1 1 I
+X enable1 5 2150 1500 200 R 50 50 1 1 I
+X enable0 6 2150 1400 200 R 50 50 1 1 I
+X test_mode0 7 2150 1300 200 R 50 50 1 1 I
+X gated_clk3 8 3550 1900 200 L 50 50 1 1 O
+X gated_clk2 9 3550 1800 200 L 50 50 1 1 O
+X gated_clk1 10 3550 1700 200 L 50 50 1 1 O
+X gated_clk0 11 3550 1600 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_VCC
+#
+DEF eSim_VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "eSim_VCC" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library

clkgatectrl/eSim Test Circuit Project Files/Clock_Gating_Controller.cir

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+* C:\Users\yamin\eSim-Workspace\Clock_Gating_Controller\Clock_Gating_Controller.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/24/26 16:55:03
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U8  Net-_U8-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U16-Pad1_ Net-_U17-Pad1_ Net-_U18-Pad1_ Net-_U19-Pad1_ clock_gating_controller_ip		
+U9  clk Net-_U8-Pad1_ adc_bridge_1		
+U10  rst_n Net-_U10-Pad2_ adc_bridge_1		
+U11  enable3 Net-_U11-Pad2_ adc_bridge_1		
+U12  enable2 Net-_U12-Pad2_ adc_bridge_1		
+U13  enable1 Net-_U13-Pad2_ adc_bridge_1		
+U14  enable0 Net-_U14-Pad2_ adc_bridge_1		
+U15  test_mode Net-_U15-Pad2_ adc_bridge_1		
+U16  Net-_U16-Pad1_ gated_clk3 dac_bridge_1		
+U17  Net-_U17-Pad1_ gated_clk2 dac_bridge_1		
+U18  Net-_U18-Pad1_ gated_clk1 dac_bridge_1		
+U19  Net-_U19-Pad1_ gated_clk0 dac_bridge_1		
+v1  clk GND pulse		
+v2  rst_n GND pulse		
+v3  enable3 GND pulse		
+v4  enable2 GND pulse		
+v5  enable1 GND pulse		
+v6  enable0 GND pulse		
+U20  gated_clk3 plot_v1		
+U21  gated_clk2 plot_v1		
+U22  gated_clk1 plot_v1		
+U23  gated_clk0 plot_v1		
+v7  ? GND pulse		
+U2  rst_n plot_v1		
+U3  enable3 plot_v1		
+U4  enable2 plot_v1		
+U5  enable1 plot_v1		
+U6  enable0 plot_v1		
+U7  test_mode plot_v1		
+U1  clk plot_v1		
+v8  VCC GND DC		
+
+.end

clkgatectrl/eSim Test Circuit Project Files/Clock_Gating_Controller.cir.out

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+* c:\users\yamin\esim-workspace\clock_gating_controller\clock_gating_controller.cir
+
+* u8  net-_u8-pad1_ net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ net-_u19-pad1_ clock_gating_controller_ip
+* u9  clk net-_u8-pad1_ adc_bridge_1
+* u10  rst_n net-_u10-pad2_ adc_bridge_1
+* u11  enable3 net-_u11-pad2_ adc_bridge_1
+* u12  enable2 net-_u12-pad2_ adc_bridge_1
+* u13  enable1 net-_u13-pad2_ adc_bridge_1
+* u14  enable0 net-_u14-pad2_ adc_bridge_1
+* u15  test_mode net-_u15-pad2_ adc_bridge_1
+* u16  net-_u16-pad1_ gated_clk3 dac_bridge_1
+* u17  net-_u17-pad1_ gated_clk2 dac_bridge_1
+* u18  net-_u18-pad1_ gated_clk1 dac_bridge_1
+* u19  net-_u19-pad1_ gated_clk0 dac_bridge_1
+v1  clk gnd pulse(0 5 0.25 0 0 0.25 0.5)
+v2  rst_n gnd pulse(0 5 0.25 0 0 1.75 3.5)
+v3  enable3 gnd pulse(0 5 0.5 0 0 0.5 1)
+v4  enable2 gnd pulse(0 5 1 0 0 1 2)
+v5  enable1 gnd pulse(5 0 1 0 0 1 2)
+v6  enable0 gnd pulse(0 5 1 0 0 1 2)
+* u20  gated_clk3 plot_v1
+* u21  gated_clk2 plot_v1
+* u22  gated_clk1 plot_v1
+* u23  gated_clk0 plot_v1
+v7  ? gnd pulse(0 5 0.5 0 0 0.5 1)
+* u2  rst_n plot_v1
+* u3  enable3 plot_v1
+* u4  enable2 plot_v1
+* u5  enable1 plot_v1
+* u6  enable0 plot_v1
+* u7  test_mode plot_v1
+* u1  clk plot_v1
+v8 vcc gnd  dc 5
+a1 [net-_u8-pad1_ ] [net-_u10-pad2_ ] [net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u14-pad2_ ] [net-_u15-pad2_ ] [net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ net-_u19-pad1_ ] u8
+a2 [clk ] [net-_u8-pad1_ ] u9
+a3 [rst_n ] [net-_u10-pad2_ ] u10
+a4 [enable3 ] [net-_u11-pad2_ ] u11
+a5 [enable2 ] [net-_u12-pad2_ ] u12
+a6 [enable1 ] [net-_u13-pad2_ ] u13
+a7 [enable0 ] [net-_u14-pad2_ ] u14
+a8 [test_mode ] [net-_u15-pad2_ ] u15
+a9 [net-_u16-pad1_ ] [gated_clk3 ] u16
+a10 [net-_u17-pad1_ ] [gated_clk2 ] u17
+a11 [net-_u18-pad1_ ] [gated_clk1 ] u18
+a12 [net-_u19-pad1_ ] [gated_clk0 ] u19
+* Schematic Name:                             clock_gating_controller_ip, NgSpice Name: clock_gating_controller_ip
+.model u8 clock_gating_controller_ip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0.001e-00 2e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(gated_clk3)
+plot v(gated_clk2)
+plot v(gated_clk1)
+plot v(gated_clk0)
+plot v(rst_n)
+plot v(enable3)
+plot v(enable2)
+plot v(enable1)
+plot v(enable0)
+plot v(test_mode)
+plot v(clk)
+
+set xbrushwidth = 3
+ plot v(gated_clk0)+20 v(gated_clk1)+40 v(gated_clk2)+60 v(gated_clk3)+ 80 v(test_mode)+ 100 v(enable0)+ 120  v(enable1)+ 140 v(enable2)+ 160 v(enable3)+ 180 v(rst_n)+ 200 v(clk) + 220
+
+.endc
+.end