Added Multiple Digital Verilog IPs

[Yamini-Menda-git]

Added the following Verilog IPs:

• Clock Gating Controller
• Interrupt Controller
• Programmable Timer
• SERDES
• Universal Shift Register
• Handshake Pulse Synchronizer
• Debounce Controller
• Round Robin Arbiter

Each IP includes:

• Verilog source files
• eSim test circuit project files
• README documentation