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FOSSEE / eSim-IP-Library Public

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Fork 12
Star 7

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Added Multiple Digital Verilog IPs#7

Open

Yamini-Menda-git wants to merge 8 commits into

FOSSEE:masterFOSSEE/eSim-IP-Library:masterfrom

Yamini-Menda-git:masterYamini-Menda-git/eSim-IP-Library:masterCopy head branch name to clipboard

Conversation Commits8 (8)Checks Files changed

Open

Added Multiple Digital Verilog IPs#7
Yamini-Menda-git wants to merge 8 commits into
FOSSEE:masterfrom
Yamini-Menda-git:master

Commits

Commits on May 28, 2026

Add Clock Gating Controller IP
Yamini-Menda-git
committed
Add Interrupt Controller IP
Yamini-Menda-git
committed
Add Programmable Timer IP
Yamini-Menda-git
committed
Add SERDES IP
Yamini-Menda-git
committed
Add Universal Shift Register IP
Yamini-Menda-git
committed
Add Handshake Pulse Synchronizer IP
Yamini-Menda-git
committed
Add Debounce Controller IP
Yamini-Menda-git
committed
Add Round Robin Arbiter IP
Yamini-Menda-git
committed

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