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ASoC: SOF: Intel: hda: follow strict BDLE address alignment for ACE4 #5684

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ASoC: SOF: Intel: hda: follow strict BDLE address alignment for ACE4 #5684

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ASoC: SOF: Intel: hda: follow strict BDLE address alignment for ACE4
kv2019i Mar 5, 2026
4f36889
ALSA: hda/intel: enforce stricter period-size alignment for Intel NVL
kv2019i Mar 9, 2026
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7 changes: 5 additions & 2 deletions sound/hda/controllers/intel.c
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Original file line number Diff line number Diff line change
Expand Up @@ -295,6 +295,9 @@ enum {
#define AZX_DCAPS_INTEL_LNL \
(AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS)

#define AZX_DCAPS_INTEL_NVL \
(AZX_DCAPS_INTEL_LNL & ~AZX_DCAPS_NO_ALIGN_BUFSIZE)

/* quirks for ATI SB / AMD Hudson */
#define AZX_DCAPS_PRESET_ATI_SB \
(AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
Expand Down Expand Up @@ -2553,8 +2556,8 @@ static const struct pci_device_id azx_ids[] = {
/* Wildcat Lake */
{ PCI_DEVICE_DATA(INTEL, HDA_WCL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
/* Nova Lake */
{ PCI_DEVICE_DATA(INTEL, HDA_NVL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
{ PCI_DEVICE_DATA(INTEL, HDA_NVL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) },
{ PCI_DEVICE_DATA(INTEL, HDA_NVL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_NVL) },
{ PCI_DEVICE_DATA(INTEL, HDA_NVL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_NVL) },
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@ujfalusi ujfalusi Mar 9, 2026

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this will not apply at 9c3af1b (v6.19) because NVL is added later: 7f42828 (v7.0-rc1)

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@kv2019i kv2019i Mar 9, 2026

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Ack fixed in V3

/* Apollolake (Broxton-P) */
{ PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
/* Gemini-Lake */
Expand Down
14 changes: 12 additions & 2 deletions sound/soc/sof/intel/hda-pcm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -219,6 +219,7 @@ EXPORT_SYMBOL_NS(hda_dsp_pcm_pointer, "SND_SOC_SOF_INTEL_HDA_COMMON");
int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream)
{
const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata);
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_component *scomp = sdev->component;
Expand Down Expand Up @@ -268,8 +269,17 @@ int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
return -ENODEV;
}

/* minimum as per HDA spec */
snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
/*
* Set period size constraint to ensure BDLE buffer length and
* start address alignment requirements are met. Align to 128
* bytes for newer Intel platforms, with older ones using 4 byte alignment.
*/
if (chip_info->hw_ip_version >= SOF_INTEL_ACE_4_0)
snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 128);
else
snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);

/* avoid circular buffer wrap in middle of period */
snd_pcm_hw_constraint_integer(substream->runtime,
Expand Down
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