fix(opt): regalloc clobbers parameter registers — AAPCS violation in i64 ops

[avrabe]

Summary

• The optimized lowering path (optimizer_bridge::ir_to_arm) hardcoded every i64 opcode to use R0:R1 / R2:R3 — regardless of whether those AAPCS arg slots still held live params. Any function that emitted an i64 op (e.g. i64.const) before reading all its i32 params would clobber R0/R1 on the very first instruction.
• Replace the hardcoding with alloc_i64_pair, a helper that picks a free callee-saved pair from [(R4,R5), (R6,R7), (R8,R9), (R10,R11)] and skips anything in vreg_to_arm.values(), local_to_reg.values(), or the reserved AAPCS slots R0..R(min(num_params,4)).
• Source operands are now resolved through vreg_to_arm instead of assumed pinned. The function epilogue emits the explicit (R0, R1) move for i64 results since they no longer pre-land at R0:R1.
• Touches every i64 op handler in the optimized path; the no-optimize path (instruction_selector.rs) is untouched (separate fix already on the parent branch).

Repro / before-after

Minimal repro /tmp/match_gale.wat — 3 i32 params, an i64 local, an i64.const 1 prologue:

Before:

00000000 <match_gale>:
   0:  movs  r0, #1   ; <-- destroys param 0
   2:  movs  r1, #0   ; <-- destroys param 1
   ...
   c:  cmp   r0, r1   ; reads garbage

After:

00000000 <match_gale>:
   0:  movs  r4, #1
   2:  movs  r5, #0
   ...
   c:  cmp   r0, r1   ; params intact

gale_k_sem_give_decide from the engine_control bench wasm:

Before: started with movs r0, #1; movs r1, #0 (clobbering 2 params).
After: starts with movs r4, #1; movs r5, #0 (params preserved).

Test plan

• cargo build --release --bin synth — clean
• cargo test --workspace — green (no failures, contracts:: tests pass on this rev)
• Repro /tmp/match_gale.wat — first instr is movs r4, #1, params intact
• Bench wasm gale_ffi.loom.wasm — gale_k_sem_give_decide no longer clobbers R0/R1
• Renode CI re-run on the engine_control bench (depends on environment — recommend triggering after merge)

Notes / scope

• Diff is ~790 insertions / ~293 deletions, over the 400 LOC soft cap noted in the task spec. The bulk of the additions are mechanical: every i64 handler had to switch from dest_lo, dest_hi, .. to listing all 6 source-vreg fields explicitly so we can resolve them through vreg_to_arm. Real new logic (alloc helper, epilogue update, Clz/Ctz/Popcnt hi-reg dance) is ~150 LOC; the rest is field-name verbosity. Architectural rewrite of the optimized path would be a bigger project than what this PR is scoped for.

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