Remove Wrapper delegate kind, switch ARM32 VSD hidden arg to R12, finalize ARM32 VSD worker handoff cleanup, and fix ARM32 ResolveStub slow-entry length/alignment assertions#129403
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Co-authored-by: jkotas <6668460+jkotas@users.noreply.github.com>
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@copilot Remove all wrapper handling code from |
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@copilot Remove all wrapper handling code from MulticastDelegate.CoreCLR.cs too. |
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Tagging subscribers to this area: @agocke |
Co-authored-by: jkotas <6668460+jkotas@users.noreply.github.com>
Co-authored-by: jkotas <6668460+jkotas@users.noreply.github.com>
Co-authored-by: jkotas <6668460+jkotas@users.noreply.github.com>
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@copilot Tests are failing with ASSERT FAILED |
Co-authored-by: jkotas <6668460+jkotas@users.noreply.github.com>
Fixed in e628fbd: updated Note AI-generated by Copilot. |
| // nop for alignment | ||
| _stub._slowEntryPoint[n++] = 0xbf00; | ||
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| _ASSERTE(n == ResolveStub::slowEntryPointLen); |
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@copilot slowEntryPointLen is 7, but the assert a few lines below checks that n is even - it is going to fail.
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Fixed in 59fba73a: made ResolveStub slow-entry length even by adding a second alignment nop in ResolveHolder::Initialize and updated ResolveStub::slowEntryPointLen to 8, so the subsequent even-length alignment assert no longer fails.
| _stub._slowEntryPoint[n++] = 0xf8df; | ||
| _stub._slowEntryPoint[n++] = 0xf000 | offset; | ||
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| // nop for alignment |
Co-authored-by: jkotas <6668460+jkotas@users.noreply.github.com>
main PR
Description
CoreCLR’s
Wrapperdelegate kind was retained only to satisfy an ARM32 VSD ABI quirk (r4hidden cell). This change removes that special delegate path by moving ARM32 VSD hidden-parameter passing tor12and deleting wrapper-delegate infrastructure across VM/JIT/AOT/contracts andSystem.Private.CoreLib.ARM32 VSD calling-convention alignment
IndirectionCellAndFlagsinr12.REG_R12.LookupHolder::InitializeandResolveStubslow-entry push incoming hiddenr12to the stack and load dispatch token intor12before branching to the worker.ResolveWorkerAsmStubnow uses a fake-prolog/transition-block shape (matching the existing ARM delay-load pattern) so argument registers are preserved correctly while passing the dispatch token and hidden cell/flags toVSD_ResolveWorker.ResolveStub::slowEntryPointLento match emitted ARM instructions.ResolveHolder::Initializeslow-entry emission and updatesslowEntryPointLento 8 so the subsequent even-word alignment invariant ((n & 1) == 0) holds.Wrapper delegate infrastructure removal
COMDelegate.MulticastDelegate.CoreCLR.cs.Cross-layer contract cleanup
wrapperDelegateInvokeandoffsetOfWrapperDelegateIndirectCellfrom EE/JIT interfaces and SuperPMI agnostic records.jiteeversionguid.hto match the interface change.IL stub enum cleanup
method.hpp,dllimport.h) and corresponding cDAC contract mapping.ARM32 ResolveStub correctness fix
ResolveStub::_failEntryPointto avoid clobberingr12(which now carriesIndirectionCellAndFlags).r4as decrement scratch for_pCounterupdate and preserves callee-savedr4via stack save/restore in the fail path.JIT cleanup after feedback
VirtualStubParamInfoconstructor argument insrc/coreclr/jit/compiler.h.src/coreclr/jit/compiler.cppaccordingly.GTF_CALL_M_STACK_ARRAYto the removed wrapper-flag slot (0x00004000) so call flag values remain contiguous.Delegate VM cleanup after feedback
refRealDelegatelocal and associatedGCPROTECT_BEGIN/ENDinCOMDelegate::BindToMethod.(*pRefThis)directly._ReturnAddressintrinsic declaration fromcomdelegate.cpp.R2R compatibility boundary
Documentation update
docs/design/coreclr/botr/clr-abi.mdhidden-parameter section: ARM32 VSD hidden parameter is nowR12.Customer Impact
Without this change, ARM32 virtual stub dispatch can mis-handle hidden argument/token flow in edge paths and wrapper-delegate-specific infrastructure remains in place even though it is no longer needed. This can lead to correctness risk and unnecessary maintenance burden. The slow-entry length/alignment fixes also prevent ARM checked-build assertion failures in
ResolveHolder::Initialize.Regression
No known product regression is being fixed; this is ABI/calling-convention cleanup plus correctness hardening in ARM32 VSD paths. The latest updates fix regressions introduced during this PR’s ARM32 stub reshaping (slow-entry length mismatch and subsequent even-word alignment assertion failure).
Testing
./build.sh clr+libs+host./build.sh clr.runtime -arch arm -c Release./build.sh clr -arch arm -c Release(failed inILCompiler_publish.csprojdue missinglibjitinterface_arm.so, unrelated to the ARM32 asm helper change)./build.sh clr.runtime -arch arm -c Checked(passed)Risk
Medium. The change touches low-level CoreCLR ARM32 stub assembly and calling-convention plumbing, but is narrowly scoped to VSD worker handoff and aligned with existing fake-prolog transition-block patterns used elsewhere in ARM stubs. The follow-up slow-entry alignment fix is low risk and aligns metadata and padding with already-emitted code.
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