Improve x86 flag lifting semantics#8300
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Jun 30, 2026
Expand x86 LLIL flag modeling for arithmetic, test, rotate, shift, double-shift, and signed multiply instructions. Add popcnt-based parity calculation, auxiliary-carry formulas, SBB/ADC carry and overflow handling, IMUL truncation checks, and count-sensitive CF/OF behavior for shifts and rotates. Use LLIL unknown for architecturally undefined flags. Fix several flag correctness issues, including PTEST/VPTEST flag polarity and cleared flags, CCMP/CTEST signed-not-less conditions, EVEX default flag values, and SHLD/SHRD count/result flag behavior. Keep variable-count register shift and rotate value lifts clean by moving count-zero/count-one flag handling into flag callbacks, while preserving count-zero no-op behavior for memory destinations. Also improve ENTER lifting for nonzero nesting levels.
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Summary
This improves x86 LLIL flag lifting coverage and correctness across arithmetic, test, rotate, shift, double-shift, and signed multiply instructions. It replaces previously unimplemented or ad hoc flag behavior with proper flag-system callbacks where possible, using newer LLIL operations such as
POPCNT(for PF) andUnknown(to model flags that are expectedly undefined).Changes
POPCNT.LLIL_UNKNOWN.ADCSBBIMULROL/RORRCL/RCRSHL/SALSHRSARSHLDSHRD0preserves destination/flags1uses defined OF behavior0PTEST/VPTEST:SetFlagwritesCCMPNL/CTESTNLnow use signed greater-or-equalSHLD/SHRDissues:ENTERlifting for nonzero nesting levels by emitting the frame pointer display setup described by the instruction semantics.Testing
I've constructed the attached binary that contains each affected instruction along with
lahfandsetoto ensure that flags are consumed and emitted during lifting for observation. I've also tested with other binaries shared by users.x86_flag_lift_variants.zip
Closes #4044