feat[bsp][xuantie]: c/r serial cpus support SMP;

.github/ALL_BSP_COMPILE.json

@@ -491,15 +491,15 @@
       "RTT_BSP": "xuantie",
       "RTT_TOOL_CHAIN": "sourcery-Xuantie-900-gcc-elf-newlib",
       "SUB_RTT_BSP": [
-        "xuantie/smartl/e901",
+        "xuantie/smartl/e901plus",
         "xuantie/smartl/e902",
         "xuantie/smartl/e906",
         "xuantie/smartl/e907",
         "xuantie/xiaohui/c906",
         "xuantie/xiaohui/c907",
         "xuantie/xiaohui/c908",
         "xuantie/xiaohui/c908x",
-        "xuantie/xiaohui/c910",
+        "xuantie/xiaohui/c920",
         "xuantie/xiaohui/r908",
         "xuantie/xiaohui/r910",
         "xuantie/xiaohui/r920"

bsp/README.md

@@ -773,14 +773,15 @@ This document is based on the RT-Thread mainline repository and categorizes the
 
 | BSP Name | GPIO | UART | ADC | I2C | SPI | WDT |
 |----------|------|------|-----|-----|-----|-----|
-| [e901](xuantie/smartl/e901) | - | ✅ | - | - | - | - |
+| [e901plus](xuantie/smartl/e901plus) | - | ✅ | - | - | - | - |
 | [e902](xuantie/smartl/e902) | - | ✅ | - | - | - | - |
 | [e906](xuantie/smartl/e906) | - | ✅ | - | - | - | - |
 | [e907](xuantie/smartl/e907) | - | ✅ | - | - | - | - |
 | [c906 (RT-Smart)](xuantie/virt64/c906) | - | ✅ | - | - | - | - |
 | [c907](xuantie/xiaohui/c907) | - | ✅ | - | - | - | - |
 | [c908](xuantie/xiaohui/c908) | - | ✅ | - | - | - | - |
-| [c910](xuantie/xiaohui/c910) | - | ✅ | - | - | - | - |
+| [c908x](xuantie/xiaohui/c908x) | - | ✅ | - | - | - | - |
+| [c920](xuantie/xiaohui/c920) | - | ✅ | - | - | - | - |
 | [r908](xuantie/xiaohui/r908) | - | ✅ | - | - | - | - |
 | [r910](xuantie/xiaohui/r910) | - | ✅ | - | - | - | - |
 | [r920](xuantie/xiaohui/r920) | - | ✅ | - | - | - | - |

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl.ld

@@ -24,13 +24,13 @@
  ******************************************************************************/
 MEMORY
 {
-    ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x20000   /* ISRAM 128KB*/
-    DSRAM : ORIGIN = 0x20000000 , LENGTH = 0x80000   /* DSRAM 512KB*/
+    ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x30000   /* ISRAM 192KB*/
+    DSRAM : ORIGIN = 0x20000000 , LENGTH = 0xC0000   /* DSRAM 768KB*/
     SRAM :  ORIGIN = 0x60000000 , LENGTH = 0x20000   /* SRAM 128KB, no cacheable*/
 }
 
 __min_heap_size = 0x200;
-PROVIDE (__ram_end  = 0x20080000);
+PROVIDE (__ram_end  = 0x200C0000);
 PROVIDE (__heap_end = __ram_end);
 
 REGION_ALIAS("REGION_TEXT",    ISRAM);
@@ -47,6 +47,7 @@ SECTIONS
   KEEP(*startup.o(*.text))
   KEEP(*startup.o(*.vectors))
   KEEP(*vectors.o(*.text))
+  KEEP(*whetstone.o(*.text))
   KEEP(*(.text.entry))
   *(.text*)
   *(.gnu.warning)
@@ -64,6 +65,12 @@ SECTIONS
   . = ALIGN(0x10) ;
   __etext = . ;
  } > REGION_TEXT
+ .eh_frame_hdr : {
+  *(.eh_frame_hdr)
+ } > REGION_TEXT
+ .eh_frame : ONLY_IF_RO {
+  KEEP (*(.eh_frame))
+ } > REGION_TEXT
  .rodata : {
   . = ALIGN(0x4) ;
   __srodata = .;
@@ -189,7 +196,7 @@ SECTIONS
   KEEP(*(*.post_driver_entry))
   __post_driver_end__ = .;
 /************** end of drivers *********/
-  . = ALIGN(0x4) ;
+  . = ALIGN(0x8) ;
   __erodata = .;
   __rodata_end__ = .;
  } > REGION_RODATA
@@ -231,10 +238,10 @@ SECTIONS
   . = ALIGN(0x4) ;
   __ram_code_end__ = .;
  } > REGION_DATA AT > REGION_RODATA
- .bss : {
-  . = ALIGN(0x4) ;
-  __sbss = ALIGN(0x4) ;
+ .bss : ALIGN(0x20) {
+  __sbss = . ;
   __bss_start__ = . ;
+  KEEP(*linpack.o(*.bss*))
   *(.dynsbss)
   *(.sbss)
   *(.sbss.*)

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h

@@ -25,26 +25,14 @@
 #ifndef __RISCV_ASM_MACRO_H__
 #define __RISCV_ASM_MACRO_H__
 
-#if (!defined(__riscv_flen)) && (CONFIG_CHECK_FPU_DIRTY)
-#error "this cpu doesn't supprot FPU, but macro 'CONFIG_CHECK_FPU_DIRTY' is defined, please remove it."
-#endif
-
-#if (!defined(__riscv_vector)) && (CONFIG_CHECK_VECTOR_DIRTY)
-#error "this cpu doesn't supprot vector, but macro 'CONFIG_CHECK_VECTOR_DIRTY' is defined, please remove it."
-#endif
-
-#if (!defined(__riscv_matrix) && !defined(__riscv_xtheadmatrix)) && (CONFIG_CHECK_MATRIX_DIRTY)
-#error "this cpu doesn't supprot matrix, but macro 'CONFIG_CHECK_MATRIX_DIRTY' is defined, please remove it."
-#endif
-
+#include <rtconfig.h>
 #include "riscv_csr.h"
 
-#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY
 .macro RESTORE_MSTATUS
     /* t0 and t1 are not restored before using */
     /* now, sp is at the top of the stack (the lowest address)*/
     li       t1, 0
-#if __riscv_matrix || __riscv_xtheadmatrix  /* matrix registers */
+#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX) /* matrix registers */
 #if __riscv_xlen == 64
     addi     t1, t1, (12 + 12)
 #else
@@ -55,7 +43,7 @@
     add      t1, t1, t0
 #endif /* __riscv_matrix || __riscv_xtheadmatrix */
 
-#ifdef __riscv_vector /* vector registers */
+#if __riscv_vector && defined(ARCH_RISCV_VECTOR) /* vector registers */
     csrr     t0, vlenb
     slli     t0, t0, 5
     add      t1, t1, t0
@@ -66,6 +54,7 @@
 #endif  /* __riscv_xlen */
 #endif  /* __riscv_vector */
 
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64 /* float registers */
 #if __riscv_xlen == 64
     addi     t1, t1, 168
@@ -76,8 +65,9 @@
 #elif __riscv_flen == 32
     addi     t1, t1, 84
 #endif /* __riscv_flen */
+#endif
 
-#ifdef __riscv_dsp  /* vxsat register, 32-bit cpu only */
+#if __riscv_dsp && defined(ARCH_RISCV_DSP) /* vxsat register, 32-bit cpu only */
     addi     t1, t1, 4
 #endif /* __riscv_dsp */
 
@@ -86,19 +76,18 @@
 #elif __riscv_xlen == 32
     addi     t1, t1, 72
 #endif
-    add      sp, sp, t1
+    add      t1, sp, t1
 
-    /* now, sp is the position of mstatus */
-    load_x   t3, (0)(sp)
+    /* now, t1 is the position of mstatus */
+    load_x   t3, (0)(t1)
     csrw     mstatus, t3
-    sub      sp, sp, t1
 .endm
 
 .macro RESTORE_SSTATUS
     /* t0 and t1 are not restored before using */
     /* now, sp is at the top of the stack (the lowest address)*/
     li       t1, 0
-#if __riscv_matrix || __riscv_xtheadmatrix /* matrix registers */
+#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX) /* matrix registers */
 #if __riscv_xlen == 64
     addi     t1, t1, (12 + 12)
 #else
@@ -109,7 +98,7 @@
     add      t1, t1, t0
 #endif /* __riscv_matrix || __riscv_xtheadmatrix */
 
-#ifdef __riscv_vector /* vector registers */
+#if __riscv_vector && defined(ARCH_RISCV_VECTOR) /* vector registers */
     csrr     t0, vlenb
     slli     t0, t0, 5
     add      t1, t1, t0
@@ -120,6 +109,7 @@
 #endif  /* __riscv_xlen */
 #endif  /* __riscv_vector */
 
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64 /* float registers */
 #if __riscv_xlen == 64
     addi     t1, t1, 168
@@ -130,26 +120,24 @@
 #elif __riscv_flen == 32
     addi     t1, t1, 84
 #endif /* __riscv_flen */
+#endif
 
 #if __riscv_xlen == 64  /*general purpose registers*/
     addi     t1, t1, (72 + 72)
 #elif __riscv_xlen == 32
     addi     t1, t1, 72
 #endif
-    add      sp, sp, t1
+    add      t1, sp, t1
 
-    /* now, sp is the position of mstatus */
-    load_x   t3, (0)(sp)
+    /* now, t1 is the position of mstatus */
+    load_x   t3, (0)(t1)
     csrw     sstatus, t3
-    sub      sp, sp, t1
 .endm
 
-#endif /* CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY */
-
 .macro SAVE_VECTOR_REGISTERS
     /* t0,t1 saved before using */
     /* mstatus->t3 */
-#ifdef __riscv_vector
+#if __riscv_vector && defined(ARCH_RISCV_VECTOR)
 #if CONFIG_CHECK_VECTOR_DIRTY
     /* check if VS filed of MSTATUS is 'dirty' */
     li       t1, SR_VS_DIRTY
@@ -227,7 +215,7 @@
 
 .macro RESTORE_VECTOR_REGISTERS
     /* t0,t1,t2 not restored before using, mstatus has been restored before using */
-#ifdef __riscv_vector
+#if __riscv_vector && defined(ARCH_RISCV_VECTOR)
 #if CONFIG_CHECK_VECTOR_DIRTY
     /* check if VS filed of MSTATUS is 'dirty' */
     li       t1, SR_VS_DIRTY
@@ -304,6 +292,7 @@
 
 .macro SAVE_FLOAT_REGISTERS
     /* t0, t1 saved before using */
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64
 #if CONFIG_CHECK_FPU_DIRTY
     /* check if FS filed of MSTATUS is 'dirty' */
@@ -378,10 +367,12 @@
     fstore_x ft10,72(sp)
     fstore_x ft11,76(sp)
 #endif /*__riscv_flen */
+#endif
 #if CONFIG_CHECK_FPU_DIRTY
     j        2f
 1:
     /* don't store, move sp only */
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64
 #if __riscv_xlen == 64
     addi     sp, sp, -168
@@ -391,12 +382,14 @@
 #elif __riscv_flen == 32
     addi     sp, sp, -84
 #endif /* __riscv_xlen */
+#endif
 2:
 #endif
 .endm
 
 .macro RESTORE_FLOAT_REGISTERS
     /* t0 and t1 are not restored before using, mstatus has been restored before using */
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64
 #if CONFIG_CHECK_FPU_DIRTY
     /* check if FS filed of MSTATUS is 'dirty' */
@@ -472,10 +465,12 @@
     fscsr    t0
     addi     sp, sp, 4
 #endif /*__riscv_flen */
+#endif
 #if CONFIG_CHECK_FPU_DIRTY
     j        2f
 1:
     /* don't restore, move sp only */
+#if __riscv_flen && defined(ARCH_RISCV_FPU)
 #if __riscv_flen == 64
 #if __riscv_xlen == 64
     addi     sp, sp, 168
@@ -485,14 +480,15 @@
 #elif __riscv_flen == 32
     addi     sp, sp, 84
 #endif /* __riscv_flen */
+#endif
 2:
 #endif /* CONFIG_CHECK_FPU_DIRTY */
 .endm
 
 .macro SAVE_MATRIX_REGISTERS
     /* t0,t1 saved before using */
 
-#if __riscv_matrix || __riscv_xtheadmatrix
+#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX)
 #if CONFIG_CHECK_MATRIX_DIRTY
     /* check if FS filed of MSTATUS is 'dirty' */
     li       t1, SR_MS_DIRTY
@@ -544,7 +540,7 @@
 .macro RESTORE_MATRIX_REGISTERS
     /* t0 and t1 are not restored before using, mstatus has been restored before using */
 
-#if __riscv_matrix || __riscv_xtheadmatrix
+#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX)
 #if CONFIG_CHECK_MATRIX_DIRTY
     /* check if FS filed of MSTATUS is 'dirty' */
     li       t1, SR_MS_DIRTY

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h

@@ -69,7 +69,9 @@
 #define SR_FS_CLEAN     0x00004000UL
 #define SR_FS_DIRTY     0x00006000UL
 
-#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_R920
+#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
+    || CONFIG_CPU_XUANTIE_R920 \
+    || CONFIG_CPU_XUANTIE_C920
 #define SR_VS          0x01800000
 #define SR_VS_OFF      0x00000000
 #define SR_VS_INITIAL  0x00800000
@@ -128,17 +130,26 @@
 #define MSTATUS_MPP_SHIFT               11
 #define MSTATUS_MPP                     (3 << MSTATUS_MPP_SHIFT)
 
-#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920
+#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
+    || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \
+    || CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920
 #define MSTATUS_VS_SHIFT                23
 #else
 #define MSTATUS_VS_SHIFT                9
 #endif
 #define MSTATUS_FS_SHIFT                13
 #define MSTATUS_MS_SHIFT                25
 
-#define INSERT_FIELD(val, which, fieldval)  (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+#define INSERT_FIELD(val, which, fieldval)    (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
 
-#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V ||CONFIG_CPU_XUANTIE_C908I || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920
+#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
+    || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \
+    || CONFIG_CPU_XUANTIE_C908_V2 || CONFIG_CPU_XUANTIE_C908V_V2 || CONFIG_CPU_XUANTIE_C908I_V2 \
+    || CONFIG_CPU_XUANTIE_C908_CP_V2 || CONFIG_CPU_XUANTIE_C908V_CP_V2 || CONFIG_CPU_XUANTIE_C908I_CP_V2 \
+    || CONFIG_CPU_XUANTIE_C908_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908V_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908I_CP_XT_V2 \
+    || CONFIG_CPU_XUANTIE_C908VK_CP_V2 || CONFIG_CPU_XUANTIE_C908VK_CP_XT_V2 \
+    || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \
+    || CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920
 #define ATTR_SO                 (1ull << 4)
 #define ATTR_CA                 (1ull << 3)
 #define ATTR_BU                 (1ull << 2)

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/csi_config.h

@@ -0,0 +1,27 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CSI_CONFIG_H__
+#define __CSI_CONFIG_H__
+
+#if CONFIG_KERNEL_RTTHREAD
+#include <rtconfig.h>
+#endif
+
+
+#endif /* end of __CSI_CONFIG_H__ */