fix[stm32[SDMMC]: Optimize SDMMC timeout handling and clock divider

[wdfk-prog]

为什么提交这份PR (why to submit this PR)

STM32 SDMMC driver still has several issues in data transfer and clock configuration:

1. Data transfer completion waits by loop count, which is not robust for different transfer sizes and clock settings, and may lead to timeout or unstable behavior.
2. Cache maintenance uses global clean/invalidate operations, which is inefficient and may introduce unnecessary overhead.
3. Clock divider handling is not clear enough in different timing modes, and the initialization / normal-speed / high-speed switching logic needs improvement.
4. Some error logs are malformed and do not provide valid diagnostic information.
5. The default clock getter is not assigned when clk_get is not provided.

This PR improves the SDMMC driver behavior and makes the logic more robust and maintainable.

你的解决方案是什么 (what is your solution)

This PR mainly includes the following changes:

1. Add a default SDMMC clock getter (stm32_sdio_clk_get) and use it when board-specific clk_get is not provided.
2. Replace the fixed loop-based data transfer wait with a tick-based timeout calculation (stm32_sdmmc_calc_timeout) based on transfer size, improving timeout robustness.
3. Replace global D-Cache clean/invalidate operations with range-based cache operations to improve execution efficiency.
4. Refine SDMMC power-mode handling in rthw_sdio_iocfg() and avoid unnecessary reconfiguration when the controller should remain stopped.
5. Optimize clock divider selection logic for initialization, legacy mode, normal speed, and high speed timing.
6. Remove redundant checks and unused global object definitions.
7. Fix malformed log messages and improve code readability.
8. Update related header definitions so frequency-related macros are more consistent.

请提供验证的bsp和config (provide the config and bsp)

• BSP:

  • bsp/stm32/[please fill in your verified board path]

• .config:

  • CONFIG_BSP_USING_SDIO
  • CONFIG_RT_USING_SDIO
  • [please fill in other changed configs if applicable]

• action:

  • [please provide your fork action link]

[github-actions]

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[github-actions]

📌 Code Review Assignment

🏷️ Tag: bsp_stm32

Reviewers: Liang1795 hamburger-os wdfk-prog

Changed Files (Click to expand)

• bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdmmc.c
• bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdmmc.h

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📊 Current Review Status (Last Updated: 2026-03-16 16:11 CST)

• ⌛ Liang1795 Pending Review
• ⌛ hamburger-os Pending Review
• ⌛ wdfk-prog Pending Review

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[wdfk-prog]

• [stm32][sdmmc]Optimize execution efficiency and find the right clock division #9276

[Copilot]

Pull request overview

This PR targets the STM32 SDMMC driver to make data transfers and clock configuration more robust, replacing fragile loop-based waits and improving cache maintenance and clock/power handling.

Changes:

• Adds a default clk_get fallback and refines SDMMC clock divider selection across timing modes.
• Replaces loop-count-based data transfer completion waits with a tick-based timeout calculation.
• Switches from global D-Cache clean/invalidate to range-based cache operations and fixes malformed log messages.

Reviewed changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 6 comments.

File	Description
bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdmmc.h	Updates SDIO/SDMMC frequency-related macros and defaults used by the driver.
bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdmmc.c	Implements timeout calculation, cache range ops, power-mode handling changes, clock divider logic updates, and error/log fixes.

Comments suppressed due to low confidence (1)

bsp/stm32/libraries/HAL_Drivers/drivers/drv_sdmmc.c:304

• [performance/性能]: Cache operation uses FLUSH for both read/write; read path should prefer INVALIDATE / Cache 操作对读写都用 FLUSH，读方向建议用 INVALIDATE

English: rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, ...) is executed for any data transfer. For read transfers, flushing can unnecessarily write back dirty lines and increases bus traffic; typically you only need to invalidate the DMA buffer before/after a DMA read. Consider selecting the cache op based on data->flags (WRITE: FLUSH/CLEAN, READ: INVALIDATE).
中文：当前无论读写都执行 rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, ...)。对读方向（DMA 写内存）而言，FLUSH 可能会产生不必要的写回，增加总线开销；通常只需要在 DMA 读操作前/后对 DMA 缓冲区做 invalidate。建议根据 data->flags 区分：写使用 FLUSH/CLEAN，读使用 INVALIDATE。

    /* data pre configuration */
    if (data != RT_NULL)
    {
        rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cache_buf, data->blks * data->blksize);

        reg_cmd |= SDMMC_CMD_CMDTRANS;
        __HAL_SD_DISABLE_IT(&sdio->sdio_des.hw_sdio, SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE);
        hsd->DTIMER = HW_SDIO_DATATIMEOUT;
        hsd->DLEN = data->blks * data->blksize;
        hsd->DCTRL = (get_order(data->blksize) << 4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0);

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[Rbb666]

还有个格式化的问题：

[wdfk-prog]

还有个格式化的问题：

• 已修改

[wdfk-prog]

2026-03-16T08:17:54.7356170Z packages/RTduino-latest/libraries/buildin/SPI/SPI.cpp:68:10: error: field designator 'usage_freq' does not refer to any field in type 'struct rt_spi_configuration'
2026-03-16T08:17:54.7356844Z         .usage_freq = RT_NULL
2026-03-16T08:17:54.7357041Z          ^
2026-03-16T08:17:54.7357200Z 1 error generated.
2026-03-16T08:17:54.7357505Z scons: *** [build/packages/RTduino-latest/libraries/buildin/SPI/SPI.o] Error 1
2026-03-16T08:17:54.7357916Z scons: building terminated because of errors.
2026-03-16T08:17:54.7358383Z �[1;32mscons -c�[0m
2026-03-16T08:17:54.7360281Z ##[error]build stm32/stm32l475-atk-pandora rtduino/adafruit-aht10.attach failed.

• 无关CI报错 @Rbb666