Independent bootloader engineer at ExerionBit.

I build minimal, auditable boot paths for ESP32 RISC-V boards, with readable code, explicit control, and evidence-backed validation. Public proof today centers on ESP32-C3 real-hardware work, supported by a portable bare-metal RISC-V reference for architecture review and early port de-risking.

• First-Board Bring-Up
• Factory and Field Recovery
• Verified Boot Gate
• Architecture de-risking review

• Minimal bootloader bring-up for ESP32-C3 and other ESP32 RISC-V targets
• Portable bare-metal RISC-V reference work
• Bare-metal C and assembly
• Early board bring-up, validation, and low-level debugging
• Recovery and update baselines with deterministic behavior
• Small systems teams can audit, adapt, and fully own

• Explicit boot flow and understandable handoff behavior
• Minimal dependencies and narrow, practical scope
• Reproducible results tied to validation artifacts and known limits
• Code teams can review, modify, and carry forward without framework noise

Email: exerionbit.diego@gmail.com

If you want to start a scoped discussion, send:

• target SoC or board
• current boot blocker
• desired outcome
• expected timeline

GitHub Issues also work when the discussion is tied to a public repository.