app: boards: add WeAct STM32F446 Core board configuration#182
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digiexchris wants to merge 1 commit intoCANnectivity:mainfrom
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app: boards: add WeAct STM32F446 Core board configuration#182digiexchris wants to merge 1 commit intoCANnectivity:mainfrom
digiexchris wants to merge 1 commit intoCANnectivity:mainfrom
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Add CANnectivity application overlay and Kconfig fragment for the WeAct Studio STM32F446 Core Board (weact_stm32f446_core). The overlay wires CAN1 (PB8 RX, PB9 TX, intended for an external SN65HVD230 transceiver) to a single CANnectivity channel and exposes TIM2 as the 1 MHz hardware timestamp counter (TIM2 input clock 84 MHz at the new SYSCLK, prescaler 83). The board's default main PLL configuration produces PLL_Q = 180 MHz, which is incompatible with USB OTG FS (requires exactly 48 MHz). The overlay reconfigures the main PLL (N=336, Q=7) so PLL_Q = 48 MHz while keeping a 168 MHz SYSCLK; this avoids enabling clk48/PLLSAI which would trip an upstream Zephyr build issue on STM32F446 (LL_RCC_PLLSAI_GetMainSource is not provided by the STM32F4 HAL). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
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done! I assumed signed off by you. |
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No, it should be signed off by you. Please see https://en.wikipedia.org/wiki/Developer_Certificate_of_Origin I have an action for documenting the process for contributing to CANnectivity, apologies for not having this in place already. |
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Add CANnectivity application overlay and Kconfig fragment for the WeAct Studio STM32F446 Core Board (weact_stm32f446_core).
The overlay wires CAN1 (PB8 RX, PB9 TX, intended for an external SN65HVD230 transceiver) to a single CANnectivity channel and exposes TIM2 as the 1 MHz hardware timestamp counter (TIM2 input clock 84 MHz at the new SYSCLK, prescaler 83).
The board's default main PLL configuration produces PLL_Q = 180 MHz, which is incompatible with USB OTG FS (requires exactly 48 MHz). The overlay reconfigures the main PLL (N=336, Q=7) so PLL_Q = 48 MHz while keeping a 168 MHz SYSCLK; this avoids enabling clk48/PLLSAI which would trip an upstream Zephyr build issue on STM32F446
(LL_RCC_PLLSAI_GetMainSource is not provided by the STM32F4 HAL).