SME2/SVE/NEON heuristic - ACL#1294
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…count Signed-off-by: Damien Dooley <damien.dooley@arm.com>
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Title:
Allow runtime masking of SVE/SVE2 CPU feature exposure
Description:
This PR adds runtime control over whether ACL exposes SVE/SVE2 capabilities through arm_compute::CPUInfo. For full context, please refer to the associated ArmNN PR at: ARM-software/armnn#820
Problem statement:
ArmNN needs a way to steer ACL away from SME/SME2 and, in some cases, SVE/SVE2 kernel families when graph-level shape heuristics indicate that those paths regress performance. The regression is most visible on SME2-capable hardware under high thread count, where the hardware/resource pressure around SME2 packing can dominate the expected matmul acceleration for some Geekbench AI shapes.
High-level approach:
ACL already had runtime masking for SME/SME2 via set_sme_allowed(). This PR adds equivalent SVE/SVE2 masking:
void CPUInfo::set_sve_allowed(bool is_allowed);
When disabled, ACL reports SVE/SVE2 and related features as unavailable through:
has_sve()
has_sve2()
has_svebf16()
has_svei8mm()
has_svef32mm()
get_isa()
This lets ArmNN apply its graph-level policy while keeping ACL’s existing kernel selection mechanisms intact.
Relationship to ArmNN PR:
The ArmNN PR emits CpuAcc options such as:
SmeEnabled=false
SveEnabled=true
or:
SmeEnabled=false
SveEnabled=false
The ACL PR provides the underlying mechanism that makes those options affect runtime kernel selection.