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perf: Enable assembly kernel for QASYMM8 MAX pooling. #1278

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Merged
morgolock merged 1 commit into from
Apr 17, 2026
+33 −10
Merged

perf: Enable assembly kernel for QASYMM8 MAX pooling. #1278

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15 changes: 8 additions & 7 deletions src/cpu/kernels/internal/CpuPool2dAssemblyWrapperKernel.cpp
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2025 Arm Limited.
* Copyright (c) 2021-2026 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
Expand Down Expand Up @@ -145,9 +145,10 @@ CpuPool2dAssemblyWrapperKernel::validate(const ITensorInfo *src, const ITensorIn
if (src->data_type() == DataType::QASYMM8)
{
const bool has_padding = info.pad_stride_info.has_padding();
ARM_COMPUTE_RETURN_ERROR_ON_MSG(
!info.exclude_padding && has_padding,
"Assembly kernels do not support padding for QASYMM8 with same src/dst quantization info");
ARM_COMPUTE_RETURN_ERROR_ON_MSG(info.pool_type != PoolingType::MAX && !info.exclude_padding &&
has_padding,
"Assembly kernels only support padded MAX pooling for QASYMM8 with "
"same src/dst quantization info");
}
}
}
Expand All @@ -159,9 +160,9 @@ CpuPool2dAssemblyWrapperKernel::validate(const ITensorInfo *src, const ITensorIn
{
// If dst is not configured, the quantization info are the same
const bool has_padding = info.pad_stride_info.has_padding();
ARM_COMPUTE_RETURN_ERROR_ON_MSG(
!info.exclude_padding && has_padding,
"Assembly kernels do not support padding for QASYMM8 with same src/dst quantization info");
ARM_COMPUTE_RETURN_ERROR_ON_MSG(info.pool_type != PoolingType::MAX && !info.exclude_padding && has_padding,
"Assembly kernels only support padded MAX pooling for QASYMM8 with "
"same src/dst quantization info");
}
}
return Status{};
Expand Down
19 changes: 19 additions & 0 deletions tests/validation/NEON/PoolingLayer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -105,6 +105,16 @@ const auto pool_outside_input_dataset = zip(
make("ExcludePadding", {false, false, false, false}));
} // namespace

const auto PoolingDatasetQASYMM8PaddedMax = combine(make("Shape", {TensorShape(7U, 5U, 3U), TensorShape(8U, 7U, 5U)}),
make("PoolingType", {PoolingType::MAX}),
make("PoolingSize", {Size2D(3, 3)}),
make("PadStride", {PadStrideInfo(2, 2, 1, 1)}),
make("ExcludePadding", {false}),
make("DataType", DataType::QASYMM8),
make("DataLayout", {DataLayout::NHWC}),
make("InputQuantInfo", {QuantizationInfo(0.25f, 11)}),
make("OutputQuantInfo", {QuantizationInfo(0.25f, 11)}));

TEST_SUITE(NEON)
TEST_SUITE(PoolingLayer)

Expand Down Expand Up @@ -385,6 +395,15 @@ using NEPoolingLayerQuantizedMixedDataLayoutFixture =
PoolingLayerValidationQuantizedFixture<Tensor, Accessor, NEPoolingLayer, T, true>;

TEST_SUITE(QASYMM8)

FIXTURE_DATA_TEST_CASE(QASYMM8PaddedMax,
NEPoolingLayerQuantizedFixture<uint8_t>,
framework::DatasetMode::PRECOMMIT,
PoolingDatasetQASYMM8PaddedMax)
{
validate(Accessor(_target), _reference, tolerance_qasymm8);
}

FIXTURE_DATA_TEST_CASE(RunSmallNCHW,
NEPoolingLayerQuantizedFixture<uint8_t>,
framework::DatasetMode::PRECOMMIT,
Expand Down
9 changes: 6 additions & 3 deletions tests/validation/runtime/experimental/operators/CpuPool2d.cpp
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, 2023-2025 Arm Limited.
* Copyright (c) 2017-2021, 2023-2026 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
Expand Down Expand Up @@ -89,11 +89,12 @@ TEST_SUITE(CpuPool2d)
TensorInfo(TensorShape(27U, 13U, 2U), 1, DataType::F32), // Invalid pad/size combination
TensorInfo(TensorShape(15U, 13U, 5U), 1, DataType::F32), // Non-rectangular Global Pooling
TensorInfo(TensorShape(13U, 13U, 5U), 1, DataType::F32), // Invalid output Global Pooling
TensorInfo(TensorShape(13U, 13U, 5U), 1, DataType::QASYMM8), // Invalid exclude_padding = false with quantized type, no actual padding and NHWC
TensorInfo(TensorShape(13U, 13U, 5U), 1, DataType::QASYMM8), // Quantized NHWC without padding remains valid
TensorInfo(TensorShape(13U, 13U, 5U), 1, DataType::F32),
TensorInfo(TensorShape(1U, 16U, 1U), 1, DataType::F32),
TensorInfo(TensorShape(112, 112, 64,1), 1, DataType::F32, DataLayout::NHWC), // Mismatching number of channels
TensorInfo(TensorShape(112, 112, 64,1), 1, DataType::F32, DataLayout::NHWC), // Mismatching width
TensorInfo(TensorShape(5U, 13U, 13U, 1U), 1, DataType::QASYMM8, DataLayout::NHWC), // Padded NHWC QASYMM8 MAX with matching qinfo
}),
make("OutputInfo",{ TensorInfo(TensorShape(25U, 11U, 2U), 1, DataType::F16),
TensorInfo(TensorShape(25U, 10U, 2U), 1, DataType::F32),
Expand All @@ -106,6 +107,7 @@ TEST_SUITE(CpuPool2d)
TensorInfo(TensorShape(1U, 15U, 1U), 1, DataType::F32),
TensorInfo(TensorShape(56, 56, 64,1), 1, DataType::F32, DataLayout::NHWC),
TensorInfo(TensorShape(56, 51, 64,1), 1, DataType::F32, DataLayout::NHWC),
TensorInfo(TensorShape(5U, 7U, 7U, 1U), 1, DataType::QASYMM8, DataLayout::NHWC),
}),
make("PoolInfo", { PoolingLayerInfo(PoolingType::AVG, 3, DataLayout::NCHW, PadStrideInfo(1, 1, 0, 0)),
PoolingLayerInfo(PoolingType::AVG, 3, DataLayout::NCHW, PadStrideInfo(1, 1, 0, 0)),
Expand All @@ -118,8 +120,9 @@ TEST_SUITE(CpuPool2d)
PoolingLayerInfo(PoolingType::MAX, 2, DataLayout::NHWC, PadStrideInfo(1, 1, 0, 0), false),
PoolingLayerInfo(PoolingType::MAX,3,DataLayout::NHWC,PadStrideInfo(2,2,1,1)),
PoolingLayerInfo(PoolingType::MAX,3,DataLayout::NHWC,PadStrideInfo(2,2,1,1)),
PoolingLayerInfo(PoolingType::MAX, 3, DataLayout::NHWC, PadStrideInfo(2, 2, 1, 1), false),
}),
make("Expected", { false, false, false, false, true, false, true, false, false, false, false})),
make("Expected", { false, false, false, false, true, false, true, false, false, false, false, true})),
input_info, output_info, pool_info, expected)
{
bool is_valid = bool(arm_compute::experimental::op::CpuPool2d::validate(&input_info.clone()->set_is_resizable(false), &output_info.clone()->set_is_resizable(false), pool_info));
Expand Down