diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config
index 8f89639f0f4..06d281afd2e 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config
@@ -184,6 +184,7 @@ CONFIG_RT_VER_NUM=0x50300
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
+CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
CONFIG_ARCH_USING_HW_ATOMIC_8=y
CONFIG_ARCH_USING_HW_ATOMIC_16=y
@@ -191,7 +192,7 @@ CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_FPU=y
-CONFIG_ARCH_ARM_CORTEX_M33=y
+CONFIG_ARCH_ARM_CORTEX_M7=y
#
# RT-Thread Components
@@ -268,7 +269,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_RPMSG is not set
# CONFIG_RT_USING_BLK is not set
+# CONFIG_RT_USING_REGULATOR is not set
+# CONFIG_RT_USING_POWER_SUPPLY is not set
# CONFIG_RT_USING_VIRTIO is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_CHERRYUSB is not set
@@ -576,6 +580,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_3GPP_AMRNB is not set
# end of multimedia packages
@@ -583,6 +588,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# tools packages
#
# CONFIG_PKG_USING_VECTOR is not set
+# CONFIG_PKG_USING_SORCH is not set
+# CONFIG_PKG_USING_DICT is not set
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_MCOREDUMP is not set
# CONFIG_PKG_USING_EASYFLASH is not set
@@ -627,6 +634,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_RT_TRACE is not set
# CONFIG_PKG_USING_ZDEBUG is not set
# CONFIG_PKG_USING_RVBACKTRACE is not set
# CONFIG_PKG_USING_HPATCHLITE is not set
@@ -729,6 +737,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_HEARTBEAT is not set
# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
# CONFIG_PKG_USING_CHERRYECAT is not set
+# CONFIG_PKG_USING_EVENT_LOOP is not set
+# CONFIG_PKG_USING_THREAD_MANAGER is not set
# end of system packages
#
@@ -812,7 +822,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
-# CONFIG_PKG_USING_MM32 is not set
+
+#
+# MM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set
+# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set
+# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set
+# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set
+# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set
+# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set
+# end of MM32 HAL & SDK Drivers
#
# WCH HAL & SDK Drivers
@@ -877,9 +901,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
#
# NUVOTON Drivers
#
-# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
-# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
# end of NUVOTON Drivers
#
@@ -905,6 +927,12 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set
# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set
# end of FT32 HAL & SDK Drivers
+
+#
+# NOVOSNS Drivers
+#
+# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set
+# end of NOVOSNS Drivers
# end of HAL & SDK Drivers
#
@@ -1085,6 +1113,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest"
# CONFIG_PKG_USING_ISOTP_C is not set
# CONFIG_PKG_USING_IKUNLED is not set
# CONFIG_PKG_USING_INS5T8025 is not set
+# CONFIG_PKG_USING_IRUART is not set
# CONFIG_PKG_USING_ST7305 is not set
# CONFIG_PKG_USING_TM1668 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
@@ -1439,7 +1468,7 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM7=y
#
# On-chip Peripheral Drivers
#
-# CONFIG_BSP_USING_DMA is not set
+CONFIG_BSP_USING_DMA=y
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_USB is not set
@@ -1450,7 +1479,9 @@ CONFIG_BSP_USING_LPUART1=y
# CONFIG_BSP_LPUART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_LPUART3 is not set
# CONFIG_BSP_USING_CAN is not set
-# CONFIG_BSP_USING_FLEXSPI is not set
+CONFIG_BSP_USING_FLEXSPI=y
+CONFIG_BSP_USING_FLEXSPI1=y
+# CONFIG_BSP_USING_FLEXSPI2 is not set
# end of On-chip Peripheral Drivers
#
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/MCUX_Config.mex b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/MCUX_Config.mex
new file mode 100644
index 00000000000..9c9e2f2d84e
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/MCUX_Config.mex
@@ -0,0 +1,667 @@
+
+
+
+ MIMXRT1189xxxxx
+ MIMXRT1189CVM8C
+ ksdk2_0
+
+
+
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+
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+
+ true
+ false
+ true
+ true
+ false
+
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+ 26.03.10
+
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+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ cm7
+ true
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+ 26.03.10
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+ true
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+
+ INPUT
+
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+ true
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+ OUTPUT
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+ true
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+ true
+
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+
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+ 26.03.10
+ c_array
+
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+ N/A
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+
\ No newline at end of file
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.c
new file mode 100644
index 00000000000..778a8dcac2d
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.c
@@ -0,0 +1,738 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v20.0
+processor: MIMXRT1189xxxxx
+package_id: MIMXRT1189CVM8C
+mcu_data: ksdk2_0
+processor_version: 26.03.10
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_misc.h"
+#include "fsl_dcdc.h"
+#include "fsl_pmu.h"
+#include "fsl_clock.h"
+#include "fsl_ele_base_api.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_FlexspiClockSafeConfig
+ * Description : FLEXSPI clock source safe configuration weak function.
+ * Called before clock source configuration.
+ * Note : Users need override this function to change FLEXSPI clock source to stable source when executing
+ * code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock source
+ * to a stable clock to avoid instruction/data fetch issue during clock updating.
+ *END**************************************************************************/
+__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void)
+{
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_SetFlexspiClock
+ * Description : This function should be overridden if executing code on FLEXSPI memory(XIP).
+ * To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source.
+ * After the clock is changed and stable, move back to run on FLEXSPI.
+ * Param base : FLEXSPI peripheral base address.
+ * Param src : FLEXSPI clock source.
+ * Param divider : FLEXSPI clock divider.
+ *END**************************************************************************/
+__attribute__((weak)) void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider)
+{
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : EdgeLock_SetClock
+ * Description : Set EdgeLock clock via safe method
+ * Note : It requires specific sequence to change edgelock clock source,
+ * otherwise the soc behavior is unpredictable.
+ *END**************************************************************************/
+__attribute__((weak)) void EdgeLock_SetClock(uint8_t mux, uint8_t div)
+{
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : DCDC_SetVoltage
+ * Description : Set DCDC voltage via safe method
+ * Note : It requires specific sequence to change DCDC voltage when GDET
+ * is enabled, otherwise the soc behavior is unpredictable.
+ *END**************************************************************************/
+__attribute__((weak)) void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage)
+{
+}
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: ARM_PLL_CLK.outFreq, value: 792 MHz}
+- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: BUS_AON_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: BUS_WAKEUP_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: CAN1_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: CAN2_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: CAN3_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: CCM_CKO1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CCM_CKO2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: ECAT_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: EDGELOCK_CLK_ROOT.outFreq, value: 200 MHz}
+- {id: ENET_REFCLK_ROOT.outFreq, value: 24 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 120 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 48 MHz}
+- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 400 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 270 MHz}
+- {id: FLEXSPI_SLV_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: GPT2_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: I3C1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: I3C2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPI2C0102_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPI2C0304_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPI2C0506_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPIT3_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: LPSPI0102_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPSPI0304_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPSPI0506_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPTMR1_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: LPTMR2_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: LPTMR3_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: LPUART0102_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART0304_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART0506_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART0708_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART0910_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: LPUART1112_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: M33_CLK_ROOT.outFreq, value: 240 MHz}
+- {id: M33_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
+- {id: M7_CLK_ROOT.outFreq, value: 792 MHz}
+- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
+- {id: MAC0_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MAC1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MAC2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MAC3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MAC4_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: NETC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: OSC_24M.outFreq, value: 24 MHz}
+- {id: OSC_32K.outFreq, value: 32.768 kHz}
+- {id: OSC_RC_24M.outFreq, value: 24 MHz}
+- {id: OSC_RC_400M.outFreq, value: 400 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 24 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 24 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 24 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 24 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 24 MHz}
+- {id: SAI4_MCLK3.outFreq, value: 24 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: SWO_TRACE_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
+- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
+- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 396 MHz}
+- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
+- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
+- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
+- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
+- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 4320/11 MHz}
+- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
+- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
+- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
+- {id: TMR_1588_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: TMR_1588_REF_CLK.outFreq, value: 24 MHz}
+- {id: TPM2_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: TPM4_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: TPM5_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: TPM6_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
+- {id: WAKEUP_AXI_CLK_ROOT.outFreq, value: 240 MHz}
+settings:
+- {id: AONDomainVoltage, value: OD}
+- {id: CoreClockRootsInitializationConfig, value: selectedCore}
+- {id: SOCDomainVoltage, value: OD}
+- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
+- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
+- {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true}
+- {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '132', locked: true}
+- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
+- {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
+- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
+- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
+- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
+- {id: ANADIG_PLL.SYS_PLL2_PFD1_DIV.scale, value: '24'}
+- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
+- {id: ANADIG_PLL.SYS_PLL3_PFD0_DIV.scale, value: '22'}
+- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
+- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
+- {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
+- {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
+- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
+- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
+- {id: CCM.CLOCK_ROOT0.DIV.scale, value: '1', locked: true}
+- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
+- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT10.DIV.scale, value: '5', locked: true}
+- {id: CCM.CLOCK_ROOT10.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT11.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT11.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT12.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT12.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT13.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT13.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT14.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT14.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT15.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT15.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT16.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT16.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT17.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT17.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT18.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT18.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT19.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_OSC.OSC_RC_400M}
+- {id: CCM.CLOCK_ROOT20.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT21.DIV.scale, value: '1', locked: true}
+- {id: CCM.CLOCK_ROOT21.MUX.sel, value: ANADIG_OSC.OSC_RC_400M}
+- {id: CCM.CLOCK_ROOT22.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD2_CLK}
+- {id: CCM.CLOCK_ROOT23.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT23.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
+- {id: CCM.CLOCK_ROOT24.DIV.scale, value: '6', locked: true}
+- {id: CCM.CLOCK_ROOT24.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '6', locked: true}
+- {id: CCM.CLOCK_ROOT25.MUX.sel, value: N/A}
+- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '6', locked: true}
+- {id: CCM.CLOCK_ROOT26.MUX.sel, value: N/A}
+- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT3.MUX.sel, value: N/A}
+- {id: CCM.CLOCK_ROOT33.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT33.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT34.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT34.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT35.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT35.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '4', locked: true}
+- {id: CCM.CLOCK_ROOT4.MUX.sel, value: N/A}
+- {id: CCM.CLOCK_ROOT5.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT5.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
+- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '3', locked: true}
+- {id: CCM.CLOCK_ROOT6.MUX.sel, value: N/A}
+- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
+- {id: CCM.CLOCK_ROOT68.MUX.sel, value: N/A}
+- {id: CCM.CLOCK_ROOT7.DIV.scale, value: '240', locked: true}
+- {id: CCM.CLOCK_ROOT7.MUX.sel, value: ANADIG_OSC.OSC_24M}
+- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
+- {id: CCM.CLOCK_ROOT9.DIV.scale, value: '2', locked: true}
+- {id: CCM.CLOCK_ROOT9.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
+ .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
+ .loopDivider = 132, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
+ };
+
+const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = {
+ .mfd = 268435455, /* Denominator of spread spectrum */
+ .ss = NULL, /* Spread spectrum parameter */
+ .ssEnable = false, /* Enable spread spectrum or not */
+ };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ clock_root_config_t rootCfg = {0};
+
+ /* Init OSC RC 400M */
+ CLOCK_OSC_EnableOscRc400M();
+
+ /* Switch both core to OscRC400M first */
+#if (__CORTEX_M == 7)
+ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+#if (__CORTEX_M == 33)
+ /* When FlexSPI2 is used, CM33 root clock must be higher than 1/4
+ of FlexSPI2 root clock, so set it to OSC RC 400M(but not OSC RC 24M)
+ firstly as common setting */
+ rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg);
+#endif
+
+#if (__CORTEX_M == 7)
+ DCDC_SetVoltage(kDCDC_CORE0, kDCDC_1P0Target1P125V);
+ DCDC_SetVoltage(kDCDC_CORE1, kDCDC_1P0Target1P125V);
+ /* FBB need to be enabled in OverDrive(OD) mode */
+ PMU_EnableFBB(ANADIG_PMU, true);
+#endif
+
+ /* Config CLK_1M */
+ CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
+
+ /* Init OSC RC 24M */
+ CLOCK_OSC_EnableOscRc24M(true);
+
+ /* Config OSC 24M */
+ ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
+ /* Wait for 24M OSC to be stable. */
+ while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
+ (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
+ {
+ }
+
+ /* Call function BOARD_FlexspiClockSafeConfig() to move FlexSPI clock to a stable clock source to avoid
+ instruction/data fetch issue when updating PLL if XIP(execute code on FLEXSPI memory). */
+ BOARD_FlexspiClockSafeConfig();
+
+ /* Init Arm Pll. */
+ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+
+ /* Bypass Sys Pll1. */
+ CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
+ /* DeInit Sys Pll1. */
+ CLOCK_DeinitSysPll1();
+
+#ifndef USE_SDRAM
+ /* Init Sys Pll2. */
+ CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
+ /* Init System Pll2 pfd0. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
+#endif
+ /* Init System Pll2 pfd1. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 24);
+ /* Init System Pll2 pfd2. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
+ /* Init System Pll2 pfd3. */
+ CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
+
+#ifndef USE_HYPERRAM
+ /* Init Sys Pll3. */
+ CLOCK_InitSysPll3();
+#endif
+ /* Init System Pll3 pfd0. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22);
+ /* Init System Pll3 pfd1. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
+#ifndef USE_HYPERRAM
+ /* Init System Pll3 pfd2. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
+#endif
+ /* Init System Pll3 pfd3. */
+ CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
+
+ /* Bypass Audio Pll. */
+ CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
+ /* DeInit Audio Pll. */
+ CLOCK_DeinitAudioPll();
+
+ /* Module clock root configurations. */
+ /* Configure M7 using ARM_PLL_CLK */
+#if (__CORTEX_M == 7)
+ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
+#endif
+
+ /* Configure M33 using SYS_PLL3_CLK */
+#if (__CORTEX_M == 33)
+ rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg);
+#endif
+
+ /* Configure EDGELOCK using OSC_RC_400M */
+ EdgeLock_SetClock(kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M, 2);
+
+ /* Configure BUS_AON using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg);
+
+ /* Configure BUS_WAKEUP using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg);
+
+ /* Configure WAKEUP_AXI using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg);
+
+ /* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg);
+
+ /* Configure M33_SYSTICK using OSC_24M */
+#if (__CORTEX_M == 33)
+ rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut;
+ rootCfg.div = 240;
+ CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg);
+#endif
+
+ /* Configure M7_SYSTICK using OSC_RC_24M */
+#if (__CORTEX_M == 7)
+ rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 240;
+ CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
+#endif
+
+ /* Configure FLEXIO1 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
+
+ /* Configure FLEXIO2 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 5;
+ CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
+
+ /* Configure LPIT3 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpit3, &rootCfg);
+
+ /* Configure LPTIMER1 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Lptimer1, &rootCfg);
+
+ /* Configure LPTIMER2 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Lptimer2, &rootCfg);
+
+ /* Configure LPTIMER3 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Lptimer3, &rootCfg);
+
+ /* Configure TPM2 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Tpm2, &rootCfg);
+
+ /* Configure TPM4 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Tpm4, &rootCfg);
+
+ /* Configure TPM5 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Tpm5, &rootCfg);
+
+ /* Configure TPM6 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 3;
+ CLOCK_SetRootClock(kCLOCK_Root_Tpm6, &rootCfg);
+
+ /* Configure GPT1 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
+
+ /* Configure GPT2 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
+
+ /* Configure FLEXSPI1 using OSC_RC_400M */
+ BOARD_SetFlexspiClock(FLEXSPI1, kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M, 1U);
+
+ /* Configure FLEXSPI2 using SYS_PLL3_PFD2_CLK */
+#ifndef USE_HYPERRAM
+ BOARD_SetFlexspiClock(FLEXSPI2, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2, 1U);
+#endif
+
+ /* Configure FLEXSPI_SLV using SYS_PLL2_CLK */
+ rootCfg.mux = kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Flexspi_Slv, &rootCfg);
+
+ /* Configure CAN1 using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 6;
+ CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
+
+ /* Configure CAN2 using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 6;
+ CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
+
+ /* Configure CAN3 using SYS_PLL3_CLK */
+ rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxSysPll3Out;
+ rootCfg.div = 6;
+ CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
+
+ /* Configure LPUART0102 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart0102, &rootCfg);
+
+ /* Configure LPUART0304 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_LPUART0304_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart0304, &rootCfg);
+
+ /* Configure LPUART0506 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_LPUART0506_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart0506, &rootCfg);
+
+ /* Configure LPUART0708 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_LPUART0708_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart0708, &rootCfg);
+
+ /* Configure LPUART0910 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_LPUART0910_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart0910, &rootCfg);
+
+ /* Configure LPUART1112 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_LPUART1112_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpuart1112, &rootCfg);
+
+ /* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg);
+
+ /* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0304, &rootCfg);
+
+ /* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */
+ rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2;
+ rootCfg.div = 4;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg);
+
+ /* Configure LPSPI0102 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg);
+
+ /* Configure LPSPI0304 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_LPSPI0304_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi0304, &rootCfg);
+
+ /* Configure LPSPI0506 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_LPSPI0506_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Lpspi0506, &rootCfg);
+
+ /* Configure I3C1 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_I3C1_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_I3c1, &rootCfg);
+
+ /* Configure I3C2 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_I3C2_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_I3c2, &rootCfg);
+
+ /* Configure USDHC1 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
+
+ /* Configure USDHC2 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
+
+ /* Configure SEMC using OSC_RC_24M */
+#ifndef USE_SDRAM
+ rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
+#endif
+
+ /* Configure ADC1 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
+
+ /* Configure ADC2 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
+
+ /* Configure ACMP using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
+
+ /* Configure ECAT using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_ECAT_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Ecat, &rootCfg);
+
+ /* Configure ENET using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_ENET_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Enet, &rootCfg);
+
+ /* Configure TMR_1588 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_TMR_1588_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Tmr_1588, &rootCfg);
+
+ /* Configure NETC using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_NETC_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Netc, &rootCfg);
+
+ /* Configure MAC0 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_MAC0_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Mac0, &rootCfg);
+
+ /* Configure MAC1 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_MAC1_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Mac1, &rootCfg);
+
+ /* Configure MAC2 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_MAC2_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Mac2, &rootCfg);
+
+ /* Configure MAC3 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_MAC3_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Mac3, &rootCfg);
+
+ /* Configure MAC4 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_MAC4_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Mac4, &rootCfg);
+
+ /* Configure SAI1 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
+
+ /* Configure SAI2 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
+
+ /* Configure SAI3 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
+
+ /* Configure SAI4 using PLL_AUDIO_CLK */
+ rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxAudioPllOut;
+ rootCfg.div = 2;
+ CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
+
+ /* Configure SPDIF using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
+
+ /* Configure ASRC using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
+
+ /* Configure MIC using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
+
+ /* Configure CKO1 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
+
+ /* Configure CKO2 using OSC_RC_24M */
+ rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc24M;
+ rootCfg.div = 1;
+ CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
+
+ /* Set SAI MCLK clock source. */
+ BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI2MClk3Sel, 0);
+ BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI3MClk3Sel, 0);
+ BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk1Sel, 0);
+ BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk2Sel, 0);
+ BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk3Sel, 0);
+
+ /* Set ECAT PORT Ref clock source. */
+ BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK;
+ BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK;
+
+ /* Set NETC PORT Ref clock source. */
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK;
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK;
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK;
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK;
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK;
+
+ /* Set TMR 1588 Ref clock source. */
+ BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK;
+
+#if (__CORTEX_M == 7)
+ SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
+#else
+ SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M33);
+#endif
+}
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.h
new file mode 100644
index 00000000000..11db4bd91e5
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/clock_config.h
@@ -0,0 +1,177 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if __CORTEX_M == 7
+ #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */
+#else
+ #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */
+#endif
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */
+#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */
+#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */
+#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
+#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */
+#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */
+#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 24000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 24000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */
+#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 24000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */
+#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 0UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 0UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 24000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 400000000UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 270000000UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */
+#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */
+#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */
+#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */
+#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */
+#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */
+#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */
+#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */
+#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 24000000UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */
+#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 24000000UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */
+#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 24000000UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */
+#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */
+#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */
+#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */
+#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */
+#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */
+#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */
+#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */
+#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */
+#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */
+#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */
+#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */
+#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 24000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 24000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 24000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 24000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 24000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */
+#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 24000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 0UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 0UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 0UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 0UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 0UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */
+#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */
+#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */
+#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
+#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */
+#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */
+#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 24000000UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 24000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
+#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */
+#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */
+#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL /* Clock consumers of SYS_PLL1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 24000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */
+#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 24000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */
+#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */
+#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */
+#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */
+#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
+#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/HW_change_bottom.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/HW_change_bottom.png
new file mode 100644
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diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/MIMXRT1180_SConsript_add.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/MIMXRT1180_SConsript_add.png
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diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/flexspi_test result.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/flexspi_test result.png
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diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/pin_config.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/figures/pin_config.png
new file mode 100644
index 00000000000..d524dead37d
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diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/peripherals.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/peripherals.c
new file mode 100644
index 00000000000..1b37baa9021
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/peripherals.c
@@ -0,0 +1,94 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v15.0
+processor: MIMXRT1189xxxxx
+package_id: MIMXRT1189CVM8C
+mcu_data: ksdk2_0
+processor_version: 26.03.10
+functionalGroups:
+- name: BOARD_InitPeripherals
+ UUID: 7ee8fc36-68c9-403c-a923-44701e1362da
+ called_from_default_init: true
+ selectedCore: cm7
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
+- global_system_definitions:
+ - user_definitions: ''
+ - user_includes: ''
+ - global_init: ''
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'uart_cmsis_common'
+- type_id: 'uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8'
+- global_USART_CMSIS_common:
+ - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'gpio_adapter_common'
+- type_id: 'gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6'
+- global_gpio_adapter_common:
+ - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals functional group
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * CM7_NVIC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'CM7_NVIC'
+- type: 'nvic'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'nvic'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'CM7_NVIC'
+- config_sets:
+ - nvic:
+ - interrupt_table: []
+ - interrupts: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void CM7_NVIC_init(void) {
+} */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void)
+{
+ /* Initialize components */
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+ BOARD_InitPeripherals();
+}
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/peripherals.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/peripherals.h
new file mode 100644
index 00000000000..2a75809c906
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/peripherals.h
@@ -0,0 +1,33 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+
+void BOARD_InitPeripherals(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.c
new file mode 100644
index 00000000000..8c08ad9b281
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.c
@@ -0,0 +1,125 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v17.0
+processor: MIMXRT1189xxxxx
+package_id: MIMXRT1189CVM8C
+mcu_data: ksdk2_0
+processor_version: 26.03.10
+external_user_signals: {}
+pin_labels:
+- {pin_num: M16, pin_signal: GPIO_AD_27, label: USER_LED_CTL1, identifier: USER_LED_CTL1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_rgpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+ BOARD_InitPins();
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
+- pin_list:
+ - {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08}
+ - {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09}
+ - {pin_num: M16, peripheral: RGPIO4, signal: 'gpio_io, 27', pin_signal: GPIO_AD_27, direction: OUTPUT}
+ - {pin_num: A4, peripheral: ARM, signal: arm_trace_swo, pin_signal: GPIO_AON_11}
+ - {pin_num: A7, peripheral: FLEXSPI1, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_B2_08, software_input_on: Disable}
+ - {pin_num: D10, peripheral: FLEXSPI1, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_B2_09, software_input_on: Disable}
+ - {pin_num: A10, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_B2_10, software_input_on: Disable}
+ - {pin_num: B9, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_B2_11, software_input_on: Disable}
+ - {pin_num: A8, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_B2_12, software_input_on: Disable}
+ - {pin_num: B8, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_B2_13, software_input_on: Disable}
+ - {pin_num: D9, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA4, pin_signal: GPIO_B2_03}
+ - {pin_num: C9, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA5, pin_signal: GPIO_B2_04}
+ - {pin_num: A9, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA6, pin_signal: GPIO_B2_05}
+ - {pin_num: E8, peripheral: FLEXSPI1, signal: FLEXSPI_A_DATA7, pin_signal: GPIO_B2_06}
+ - {pin_num: A6, peripheral: FLEXSPI1, signal: FLEXSPI_A_DQS, pin_signal: GPIO_B2_07, software_input_on: Disable}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins, assigned for the Cortex-M7F core.
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+ CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */
+ CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */
+
+ /* GPIO configuration of USER_LED_CTL1 on GPIO_AD_27 (pin M16) */
+ rgpio_pin_config_t USER_LED_CTL1_config = {
+ .pinDirection = kRGPIO_DigitalOutput,
+ .outputLogic = 0U,
+ };
+ /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */
+ RGPIO_PinInit(RGPIO4, 27U, &USER_LED_CTL1_config);
+
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_03_FLEXSPI1_BUS2BIT_A_DATA04, /* GPIO_B2_03 is configured as FLEXSPI1_BUS2BIT_A_DATA04 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_04_FLEXSPI1_BUS2BIT_A_DATA05, /* GPIO_B2_04 is configured as FLEXSPI1_BUS2BIT_A_DATA05 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_05_FLEXSPI1_BUS2BIT_A_DATA06, /* GPIO_B2_05 is configured as FLEXSPI1_BUS2BIT_A_DATA06 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_06_FLEXSPI1_BUS2BIT_A_DATA07, /* GPIO_B2_06 is configured as FLEXSPI1_BUS2BIT_A_DATA07 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS, /* GPIO_B2_07 is configured as FLEXSPI1_BUS2BIT_A_DQS */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK, /* GPIO_B2_08 is configured as FLEXSPI1_BUS2BIT_A_SCLK */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B, /* GPIO_B2_09 is configured as FLEXSPI1_BUS2BIT_A_SS0_B */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00, /* GPIO_B2_10 is configured as FLEXSPI1_BUS2BIT_A_DATA00 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01, /* GPIO_B2_11 is configured as FLEXSPI1_BUS2BIT_A_DATA01 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02, /* GPIO_B2_12 is configured as FLEXSPI1_BUS2BIT_A_DATA02 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03, /* GPIO_B2_13 is configured as FLEXSPI1_BUS2BIT_A_DATA03 */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+ IOMUXC_SetPinMux(
+ IOMUXC_GPIO_AON_11_JTAG_MUX_TDO, /* GPIO_AON_11 is configured as JTAG_MUX_TDO */
+ 0U); /* Software Input On Field: Input Path is determined by functionality */
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.h
new file mode 100644
index 00000000000..7f758258719
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/pin_mux.h
@@ -0,0 +1,57 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* GPIO_AD_27 (coord M16), USER_LED_CTL1 */
+/* Routed pin properties */
+#define BOARD_INITPINS_USER_LED_CTL1_PERIPHERAL RGPIO4 /*!< Peripheral name */
+#define BOARD_INITPINS_USER_LED_CTL1_SIGNAL gpio_io /*!< Signal name */
+#define BOARD_INITPINS_USER_LED_CTL1_CHANNEL 27U /*!< Signal channel */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITPINS_USER_LED_CTL1_GPIO RGPIO4 /*!< GPIO peripheral base pointer */
+#define BOARD_INITPINS_USER_LED_CTL1_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
+#define BOARD_INITPINS_USER_LED_CTL1_GPIO_PIN 27U /*!< GPIO pin number */
+#define BOARD_INITPINS_USER_LED_CTL1_GPIO_PIN_MASK (1U << 27U) /*!< GPIO pin mask */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M7F */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/ports/flexspi_octal_flash_ops.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/ports/flexspi_octal_flash_ops.c
new file mode 100644
index 00000000000..3ca21f2817c
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/ports/flexspi_octal_flash_ops.c
@@ -0,0 +1,599 @@
+/*
+ * Copyright 2019-2022, 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexspi.h"
+#include "ports/flexspi_port.h"
+#include "rtconfig.h"
+
+#ifdef BSP_USING_DMA
+#include "fsl_flexspi_edma.h"
+#endif
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+extern flexspi_device_config_t deviceconfig;
+extern const uint32_t customLUTOctalMode[CUSTOM_LUT_LENGTH];
+#ifdef BSP_USING_DMA
+static volatile bool g_completionFlag = false;
+edma_handle_t dmaTxHandle;
+edma_handle_t dmaRxHandle;
+static flexspi_edma_handle_t flexspiHandle;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#ifdef BSP_USING_DMA
+static void flexspi_callback(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, status_t status, void *userData)
+{
+ /* Signal transfer success when received success status. */
+ if (status == kStatus_Success)
+ {
+ g_completionFlag = true;
+ }
+}
+#endif
+
+void flexspi_nor_disable_cache(flexspi_cache_status_t *cacheStatus)
+{
+ (void)memset(cacheStatus, 0, sizeof(flexspi_cache_status_t));
+
+#if (defined __CORTEX_M) && (__CORTEX_M == 7U)
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ /* Disable D cache. */
+ if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
+ {
+ SCB_DisableDCache();
+ cacheStatus->DCacheEnableFlag = true;
+ }
+#endif /* __DCACHE_PRESENT */
+
+#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ /* Disable I cache. */
+ if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
+ {
+ SCB_DisableICache();
+ cacheStatus->ICacheEnableFlag = true;
+ }
+#endif /* __ICACHE_PRESENT */
+
+#elif (defined FSL_FEATURE_SOC_LMEM_COUNT) && (FSL_FEATURE_SOC_LMEM_COUNT != 0U)
+ /* Disable code bus cache and system bus cache */
+ if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR))
+ {
+ L1CACHE_DisableCodeCache();
+ cacheStatus->codeCacheEnableFlag = true;
+ }
+ if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR))
+ {
+ L1CACHE_DisableSystemCache();
+ cacheStatus->systemCacheEnableFlag = true;
+ }
+
+#elif (defined FSL_FEATURE_SOC_CACHE64_CTRL_COUNT) && (FSL_FEATURE_SOC_CACHE64_CTRL_COUNT != 0U)
+ /* Disable cache */
+ CACHE64_DisableCache(EXAMPLE_CACHE);
+ cacheStatus->CacheEnableFlag = true;
+#endif
+}
+
+void flexspi_nor_enable_cache(flexspi_cache_status_t cacheStatus)
+{
+#if (defined __CORTEX_M) && (__CORTEX_M == 7U)
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if (cacheStatus.DCacheEnableFlag)
+ {
+ /* Enable D cache. */
+ SCB_EnableDCache();
+ }
+#endif /* __DCACHE_PRESENT */
+
+#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if (cacheStatus.ICacheEnableFlag)
+ {
+ /* Enable I cache. */
+ SCB_EnableICache();
+ }
+#endif /* __ICACHE_PRESENT */
+
+#elif (defined FSL_FEATURE_SOC_LMEM_COUNT) && (FSL_FEATURE_SOC_LMEM_COUNT != 0U)
+ if (cacheStatus.codeCacheEnableFlag)
+ {
+ /* Enable code cache. */
+ L1CACHE_EnableCodeCache();
+ }
+
+ if (cacheStatus.systemCacheEnableFlag)
+ {
+ /* Enable system cache. */
+ L1CACHE_EnableSystemCache();
+ }
+#elif (defined FSL_FEATURE_SOC_CACHE64_CTRL_COUNT) && (FSL_FEATURE_SOC_CACHE64_CTRL_COUNT != 0U)
+ if (cacheStatus.CacheEnableFlag)
+ {
+ /* Enable cache. */
+ CACHE64_EnableCache(EXAMPLE_CACHE);
+ }
+#endif
+}
+
+status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr, bool enableOctal)
+{
+ flexspi_transfer_t flashXfer;
+ status_t status;
+
+ /* Write enable */
+ flashXfer.deviceAddress = baseAddr;
+ flashXfer.port = FLASH_PORT;
+ flashXfer.cmdType = kFLEXSPI_Command;
+ flashXfer.SeqNumber = 1;
+ if (enableOctal)
+ {
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI;
+ }
+ else
+ {
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+ }
+
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+ return status;
+}
+
+status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base, bool enableOctal)
+{
+ /* Wait status ready. */
+ bool isBusy;
+ uint32_t readValue=0;
+ status_t status;
+ flexspi_transfer_t flashXfer;
+
+ flashXfer.deviceAddress = 0;
+ flashXfer.port = FLASH_PORT;
+ flashXfer.cmdType = kFLEXSPI_Read;
+ flashXfer.SeqNumber = 1;
+ if (enableOctal)
+ {
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI;
+ }
+ else
+ {
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS;
+ }
+
+ flashXfer.data = &readValue;
+ flashXfer.dataSize = 1;
+
+ do
+ {
+ /* For flash targets, after doing erase/program, need to call flexspi_nor_wait_bus_busy to wait for the
+ operation finish, Use blocking way to read back the status instead of using DMA. The reason is that the called
+ DMA API calls memset which is placed in flash region, because the external flash is being erase/propgram, so
+ load instruction from external flash at this time may read back some invalid instructions. */
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+ if (FLASH_BUSY_STATUS_POL)
+ {
+ if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET))
+ {
+ isBusy = true;
+ }
+ else
+ {
+ isBusy = false;
+ }
+ }
+ else
+ {
+ if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET))
+ {
+ isBusy = false;
+ }
+ else
+ {
+ isBusy = true;
+ }
+ }
+
+ } while (isBusy);
+
+ return status;
+}
+
+#if defined(FLASH_ENABLE_OCTAL_CMD)
+status_t flexspi_nor_enable_octal_mode(FLEXSPI_Type *base)
+{
+ flexspi_transfer_t flashXfer;
+ status_t status;
+
+#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
+ flexspi_cache_status_t cacheStatus;
+ flexspi_nor_disable_cache(&cacheStatus);
+#endif
+
+ uint32_t writeValue = FLASH_ENABLE_OCTAL_CMD;
+
+ /* Make sure external flash is not in busy status. */
+ status = flexspi_nor_wait_bus_busy(base, false);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ /* Write enable */
+ status = flexspi_nor_write_enable(base, 0, false);
+
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ /* Enable quad mode. */
+ flashXfer.deviceAddress = 0;
+ flashXfer.port = FLASH_PORT;
+ flashXfer.cmdType = kFLEXSPI_Write;
+ flashXfer.SeqNumber = 1;
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ENTEROPI;
+ flashXfer.data = &writeValue;
+ flashXfer.dataSize = 1;
+
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ status = flexspi_nor_wait_bus_busy(base, true);
+
+ /* Do software reset. */
+ FLEXSPI_SoftwareReset(base);
+
+#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
+ flexspi_nor_enable_cache(cacheStatus);
+#endif
+
+ return status;
+}
+#endif
+
+status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address)
+{
+ status_t status;
+ flexspi_transfer_t flashXfer;
+
+#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
+ flexspi_cache_status_t cacheStatus;
+ flexspi_nor_disable_cache(&cacheStatus);
+#endif
+
+ /* Write enable */
+ status = flexspi_nor_write_enable(base, 0, true);
+
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ flashXfer.deviceAddress = address;
+ flashXfer.port = FLASH_PORT;
+ flashXfer.cmdType = kFLEXSPI_Command;
+ flashXfer.SeqNumber = 1;
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ status = flexspi_nor_wait_bus_busy(base, true);
+
+ /* Do software reset. */
+ FLEXSPI_SoftwareReset(base);
+
+#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
+ flexspi_nor_enable_cache(cacheStatus);
+#endif
+
+ return status;
+}
+
+status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src)
+{
+#if defined(FLASH_ENABLE_OCTAL_CMD)
+ assert(((uint32_t)dstAddr & (0x1UL)) == 0UL);
+#endif
+
+ status_t status;
+ flexspi_transfer_t flashXfer;
+
+#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
+ flexspi_cache_status_t cacheStatus;
+ flexspi_nor_disable_cache(&cacheStatus);
+#endif
+
+ /* Write neable */
+ status = flexspi_nor_write_enable(base, dstAddr, true);
+
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ /* Prepare page program command */
+ flashXfer.deviceAddress = dstAddr;
+ flashXfer.port = FLASH_PORT;
+ flashXfer.cmdType = kFLEXSPI_Write;
+ flashXfer.SeqNumber = 1;
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
+ flashXfer.data = (uint32_t *)src;
+ flashXfer.dataSize = FLASH_PAGE_SIZE;
+#ifdef BSP_USING_DMA
+ g_completionFlag = false;
+ status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer);
+#else
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+#endif
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+#ifdef BSP_USING_DMA
+ /* Wait for transfer completed. */
+ while (!g_completionFlag)
+ {
+ }
+#endif
+ status = flexspi_nor_wait_bus_busy(base, true);
+
+ /* Do software reset. */
+ FLEXSPI_SoftwareReset(base);
+
+#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
+ flexspi_nor_enable_cache(cacheStatus);
+#endif
+
+ return status;
+}
+
+status_t flexspi_nor_read_data(FLEXSPI_Type *base, uint32_t startAddress, uint32_t *buffer, uint32_t length)
+{
+ status_t status;
+ flexspi_transfer_t flashXfer;
+ uint32_t readAddress = startAddress;
+
+ /* Read page. */
+ flashXfer.deviceAddress = readAddress;
+ flashXfer.port = FLASH_PORT;
+ flashXfer.cmdType = kFLEXSPI_Read;
+ flashXfer.SeqNumber = 1;
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READ;
+ flashXfer.data = buffer;
+ flashXfer.dataSize = length;
+#ifdef BSP_USING_DMA
+ g_completionFlag = false;
+
+ status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer);
+
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ /* Wait for transfer completed. */
+ while (!g_completionFlag)
+ {
+ }
+#else
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+#endif
+ return status;
+}
+
+#if defined(__ICCARM__)
+#pragma optimize = none
+#endif
+status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId)
+{
+ /* Read manufacturer ID based on JEP106V spec, max continuation code table is 9, max manufacturer ID starts from
+ * 9 + 1. */
+ uint8_t id[10] = {0x00U};
+ flexspi_transfer_t flashXfer;
+ flashXfer.deviceAddress = 0;
+ flashXfer.port = FLASH_PORT;
+ flashXfer.cmdType = kFLEXSPI_Read;
+ flashXfer.SeqNumber = 1;
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID_OPI;
+ flashXfer.data = (uint32_t *)id;
+ flashXfer.dataSize = 10U;
+
+ status_t status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+ for (uint8_t i = 0x00U; i < 10U; i++)
+ {
+ if (0x7FU != id[i])
+ {
+ *vendorId = (uint32_t)id[i];
+ break;
+ }
+ }
+
+ return status;
+}
+
+status_t flexspi_nor_erase_chip(FLEXSPI_Type *base)
+{
+ status_t status;
+ flexspi_transfer_t flashXfer;
+
+ /* Write enable */
+ status = flexspi_nor_write_enable(base, 0, true);
+
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ flashXfer.deviceAddress = 0;
+ flashXfer.port = FLASH_PORT;
+ flashXfer.cmdType = kFLEXSPI_Command;
+ flashXfer.SeqNumber = 1;
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_CHIPERASE;
+
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ status = flexspi_nor_wait_bus_busy(base, true);
+
+ return status;
+}
+
+void flexspi_nor_flash_init(FLEXSPI_Type *base)
+{
+ flexspi_config_t config;
+ /* To store custom's LUT table in local. */
+ uint32_t tempCustomLUT[CUSTOM_LUT_LENGTH] = {0U};
+
+#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
+ flexspi_cache_status_t cacheStatus;
+ flexspi_nor_disable_cache(&cacheStatus);
+#endif
+#ifdef BSP_USING_DMA
+ edma_config_t userConfig;
+
+ /* EDMA init */
+ /*
+ * userConfig.enableRoundRobinArbitration = false;
+ * userConfig.enableHaltOnError = true;
+ * userConfig.enableContinuousLinkMode = false;
+ * userConfig.enableDebugMode = false;
+ */
+ EDMA_GetDefaultConfig(&userConfig);
+#if defined(BOARD_GetEDMAConfig)
+ BOARD_GetEDMAConfig(userConfig);
+#endif
+ EDMA_Init(EXAMPLE_FLEXSPI_DMA, &userConfig);
+ /* Set request */
+ EDMA_SetChannelMux(EXAMPLE_FLEXSPI_DMA, FLEXSPI_TX_DMA_CHANNEL, FLEXSPI_TX_DMA_REQUEST_SOURCE);
+ EDMA_SetChannelMux(EXAMPLE_FLEXSPI_DMA, FLEXSPI_RX_DMA_CHANNEL, FLEXSPI_RX_DMA_REQUEST_SOURCE);
+ /* Create the EDMA channel handles */
+ EDMA_CreateHandle(&dmaTxHandle, EXAMPLE_FLEXSPI_DMA, FLEXSPI_TX_DMA_CHANNEL);
+ EDMA_CreateHandle(&dmaRxHandle, EXAMPLE_FLEXSPI_DMA, FLEXSPI_RX_DMA_CHANNEL);
+#endif
+ /* Copy LUT information from flash region into RAM region, because LUT update maybe corrupt read sequence(LUT[0])
+ * and load wrong LUT table from FLASH region. */
+ memcpy(tempCustomLUT, customLUTOctalMode, sizeof(tempCustomLUT));
+
+ /*Get FLEXSPI default settings and configure the flexspi. */
+ FLEXSPI_GetDefaultConfig(&config);
+
+ /*Set AHB buffer size for reading data through AHB bus. */
+ config.ahbConfig.enableAHBPrefetch = true;
+ config.ahbConfig.enableAHBBufferable = true;
+ config.ahbConfig.enableReadAddressOpt = true;
+ config.ahbConfig.enableAHBCachable = true;
+ config.rxSampleClock = FLEXSPI_RX_SAMPLE_CLOCK;
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
+ config.enableCombination = true;
+#endif
+ FLEXSPI_Init(base, &config);
+
+ /* Configure flash settings according to serial flash feature. */
+ FLEXSPI_SetFlashConfig(base, &deviceconfig, FLASH_PORT);
+
+ /* Update LUT table into a specific mode, such as octal SDR mode or octal DDR mode based on application's
+ * requirement. */
+ FLEXSPI_UpdateLUT(base, 0, tempCustomLUT, CUSTOM_LUT_LENGTH);
+
+ /* Do software reset. */
+ FLEXSPI_SoftwareReset(base);
+#ifdef BSP_USING_DMA
+ /* Create handle for flexspi. */
+ FLEXSPI_TransferCreateHandleEDMA(FLEXSPI1_CONTROL_BASE, &flexspiHandle, flexspi_callback, NULL, &dmaTxHandle,
+ &dmaRxHandle);
+#endif
+#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
+ flexspi_nor_enable_cache(cacheStatus);
+#endif
+}
+
+status_t flexspi_nor_flash_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src, uint32_t length)
+{
+ status_t status;
+ flexspi_transfer_t flashXfer;
+
+ /* Flash program limits program size smaller than flash page size for one program command sequence. */
+ assert(length <= FLASH_PAGE_SIZE);
+
+ /* Make sure external flash is not in busy status. */
+ status = flexspi_nor_wait_bus_busy(base, true);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ /* Write enable */
+ status = flexspi_nor_write_enable(base, dstAddr, true);
+
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ /* Prepare page program command */
+ flashXfer.deviceAddress = dstAddr;
+ flashXfer.port = FLASH_PORT;
+ flashXfer.cmdType = kFLEXSPI_Write;
+ flashXfer.SeqNumber = 1;
+ flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
+ flashXfer.data = (uint32_t *)src;
+ flashXfer.dataSize = length;
+#ifdef BSP_USING_DMA
+ g_completionFlag = false;
+
+ status = FLEXSPI_TransferEDMA(base, &flexspiHandle, &flashXfer);
+#else
+ status = FLEXSPI_TransferBlocking(base, &flashXfer);
+#endif
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+#ifdef BSP_USING_DMA
+ /* Wait for transfer completed. */
+ while (!g_completionFlag)
+ {
+ }
+#endif
+ status = flexspi_nor_wait_bus_busy(base, true);
+
+ /* Do software reset. */
+#if defined(FSL_FEATURE_SOC_OTFAD_COUNT) && defined(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) && \
+ defined(FLEXSPI_AHBCR_CLRAHBTXBUF_MASK)
+ base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK;
+ base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK);
+#else
+ FLEXSPI_SoftwareReset(base);
+#endif
+
+ return status;
+}
\ No newline at end of file
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/ports/flexspi_port.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/ports/flexspi_port.h
new file mode 100644
index 00000000000..b67a2324590
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/ports/flexspi_port.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2022-08-15 xjy198903 The first version for rt1170
+ */
+
+#ifndef FLEXSPI_PORT_H__
+#define FLEXSPI_PORT_H__
+
+#include "fsl_cache.h"
+
+/* parameters for flexpsi peripheral */
+#define FLEXSPI1_CONTROL_BASE FLEXSPI1
+
+#define FLEXSPI_ROOT_CLK (400000000U) /* serial root clk: 400MHz*/
+#define FLASH_SIZE (64 * 1024) /* device size 64*1024(KB) = 64MB */
+#define FLASH_PAGE_SIZE 256
+#define SECTOR_SIZE 0x1000 /* 4K */
+
+#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */
+#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */
+#define AWR_SEQ_NUMBER 0 /* Sequence number for AHB write command */
+#define AWR_SEQ_INDEX 0 /* Sequence ID for AHB write command */
+
+#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkExternalInputFromDqsPad
+
+#define FLASH_PORT kFLEXSPI_PortA1
+#define CLOCK_SRC kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M
+#define CLOCK_DIV 2U
+#define CUSTOM_LUT_LENGTH 60U
+
+/* DMA related. */
+#define EXAMPLE_FLEXSPI_DMA (DMA4)
+
+#define FLEXSPI_TX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Tx
+#define FLEXSPI_RX_DMA_REQUEST_SOURCE kDma4RequestMuxFlexSPI1Rx
+
+#define FLEXSPI_TX_DMA_CHANNEL 0U
+#define FLEXSPI_RX_DMA_CHANNEL 2U
+
+
+#define NOR_CMD_LUT_SEQ_IDX_READ 0
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2
+#define NOR_CMD_LUT_SEQ_IDX_READID_OPI 3
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI 4
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 6
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 7
+#define NOR_CMD_LUT_SEQ_IDX_ENTEROPI 8
+/* NOTE: Workaround for debugger.
+ Must define AHB write FlexSPI sequence index to 9 to avoid debugger issue.
+ Debugger can attach to the CM33 core only when ROM executes to certain place.
+ At that point, AHB write FlexSPI sequence index is set to 9, but in LUT, the
+ command is not filled by ROM. If the debugger sets software breakpoint at flash
+ after reset/attachment, FlexSPI AHB write command will be triggered. It may
+ cause AHB bus hang if the command in LUT sequence index 9 is any read opeartion.
+ So we need to ensure at any time, the FlexSPI LUT sequence 9 for the flash must
+ be set to STOP command to avoid unexpected debugger behaivor.
+ */
+#define NOR_CMD_LUT_SEQ_IDX_WRITE 9
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI 10
+
+#define FLASH_BUSY_STATUS_POL 1
+#define FLASH_BUSY_STATUS_OFFSET 0
+#define FLASH_ERROR_STATUS_MASK 0x0e
+
+/*
+ * If cache is enabled, this example should maintain the cache to make sure
+ * CPU core accesses the memory, not cache only.
+ */
+#define CACHE_MAINTAIN 1
+
+/*${macro:end}*/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*${variable:start}*/
+#if (defined CACHE_MAINTAIN) && (CACHE_MAINTAIN == 1)
+typedef struct _flexspi_cache_status
+{
+ volatile bool DCacheEnableFlag;
+ volatile bool ICacheEnableFlag;
+} flexspi_cache_status_t;
+#endif
+
+
+
+
+#endif /* FLEXSPI_PORT_H__ */
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/readme.txt b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/readme.txt
new file mode 100644
index 00000000000..cfbf8285d33
--- /dev/null
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config_hyperFlash/readme.txt
@@ -0,0 +1,44 @@
+## On-chip peripheral configuration of imxrt1180-nxp-evk --FlexSPI1
+
+### 1. Demo feature list
+
+- [x] use MCUX_Config software to set pin_mux, clock.
+- [x] board boots up from CMSIS-DAP. (FlexSPI1_A- QSPI Flash W25Q128 is used for CM33 XIP boot-up)
+- [x] FlexSPI1_B is set to octal mode for hyperFlash(MT35XU512ABA2G12-0AAT) reading&writing
+- [x] when BSP_USING_DMA is enabled, eDMA4 CH0 is used for TX and CH2 for RX for CPU offload.
+- [x] flexspi_test command is used for test in MSH console.
+
+### 2. Hardware configuration
+
+### 2.1 pin configuration in MCUX_Config software
+
+
+
+
+
+### 2.2 hardware change on top
+
+
+
+### 2.3 hardware change on bottom
+
+
+
+do hardware change to enable path for hyper Flash.
+
+### 2.4 chip sdk change
+
+
+
+add these codes above to "nxp-imxrt-sdk-latest/MIMXRT1180/SConscript" to enable chip specific drivers.
+
+### 3. FlexSPI1_b octal mode test
+
+
+
+### 4. limitation
+
+- only use MCUX_Config for pin_mux, clock configuration, providing enough flexibility on drv_flexspi.
+- merge official examples on FlexSPI octal polling and DMA mode for hyper Flash operation. XIP and FLASH_ADESTO are not supported.
+- Only support booting from CMSIS-DAP due to hardware limitation.
+
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript
index 81007a0eebc..be640d8c656 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript
@@ -5,11 +5,13 @@ cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
board.c
-MCUX_Config/clock_config.c
-MCUX_Config/pin_mux.c
+MCUX_Config_hyperFlash/clock_config.c
+MCUX_Config_hyperFlash/pin_mux.c
+MCUX_Config_hyperFlash/peripherals.c
+MCUX_Config_hyperFlash/ports/flexspi_octal_flash_ops.c
""")
-CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
+CPPPATH = [cwd,cwd + '/MCUX_Config_hyperFlash',cwd + '/ports']
CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm7', 'MIMXRT1189_cm7_SERIES', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1', 'ARM_MATH_CM7']
if rtconfig.PLATFORM in ['gcc']:
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c
index 0c4db043d11..4e6f93733f8 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c
@@ -12,6 +12,10 @@
#include "fsl_iomuxc.h"
#include "fsl_rgpio.h"
#include "fsl_cache.h"
+#include "fsl_ele_base_api.h"
+#include "fsl_dcdc.h"
+#include "fsl_trdc.h"
+#include "fsl_rgpio.h"
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
4 bits for subpriority */
@@ -229,6 +233,478 @@ void BOARD_ConfigMPU(void)
L1CACHE_EnableICache();
}
+void BOARD_RequestTRDC(bool bRequestAON, bool bRequestWakeup, bool bReqeustMega)
+{
+#define ELE_TRDC_AON_ID 0x74
+#define ELE_TRDC_WAKEUP_ID 0x78
+#define ELE_TRDC_MEGA_ID 0x82
+#define ELE_CORE_CM33_ID 0x1
+#define ELE_CORE_CM7_ID 0x2
+
+#if (__CORTEX_M == 33)
+ uint8_t ele_core_id = ELE_CORE_CM33_ID;
+#elif (__CORTEX_M == 7)
+ uint8_t ele_core_id = ELE_CORE_CM7_ID;
+#endif
+
+ uint32_t ele_fw_sts;
+
+ /* Get ELE FW status */
+ ELE_BaseAPI_GetFwStatus(MU_RT_S3MUA, &ele_fw_sts);
+
+ if (bRequestAON)
+ {
+ /* Release TRDC AON to current core */
+ ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ele_core_id);
+ }
+
+ /*
+ * TRDC MEGA request must be prior to TRDC WAKEUP, as TRDC MEGA access
+ * is controlled by the TRDC WAKEUP.
+ * note:
+ * If TRDC WAKEUP has been release to one core firstly, then it will fail
+ * to release TRDC MEGA to same/another core.
+ */
+ if (bReqeustMega)
+ {
+ /* Release TRDC MEGA to current core */
+ ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_MEGA_ID, ele_core_id);
+ }
+
+ if (bRequestWakeup)
+ {
+ /* Release TRDC WAKEUP to current core */
+ ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ele_core_id);
+ }
+}
+
+void APP_CommonTrdcDACSetting(void)
+{
+ trdc_processor_domain_assignment_t procAssign = {.domainId = 0U,
+ .domainIdSelect = kTRDC_DidInput,
+ .pidDomainHitConfig = kTRDC_pidDomainHitNone0,
+ .pidMask = 0U,
+ .secureAttr = kTRDC_ForceSecure,
+ .pid = 0U,
+ .lock = false
+ };
+
+ trdc_non_processor_domain_assignment_t nonProcAssign = {.domainId = 0U,
+ .privilegeAttr = kTRDC_ForcePrivilege,
+ .secureAttr = kTRDC_ForceSecure,
+ .bypassDomainId = true,
+ .lock = false
+ };
+
+ /* 1. Set the MDAC Configuration in TRDC1. */
+ /* Configure the access control for CM33(master 1 for TRDC1, MDAC_A1). */
+ procAssign.domainId = 0x2U;
+ TRDC_SetProcessorDomainAssignment(TRDC1, (uint8_t)kTRDC1_MasterCM33, 0U, &procAssign);
+ /* Configure the access control for eDMA3(master 2 for TRDC1, MDAC_A2). */
+ nonProcAssign.domainId = 0x7U;
+ TRDC_SetNonProcessorDomainAssignment(TRDC1, (uint8_t)kTRDC1_MasterDMA3, &nonProcAssign);
+
+ /* 2. Set the MDAC Configuration in TRDC2. */
+ /* Configure the access control for CM7 AHBP(master 0 for TRDC2, MDAC_W0). */
+ procAssign.domainId = 0x4U;
+ TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCM7AHBP, 0U, &procAssign);
+ /* Configure the access control for CM7 AXI(master 1 for TRDC2, MDAC_W1). */
+ TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCM7AXI, 0U, &procAssign);
+ /* Configure the access control for DAP AHB_AP_SYS(master 2 for TRDC2, MDAC_W2). */
+ nonProcAssign.domainId = 0x9U;
+ TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterDAP, &nonProcAssign);
+ /* Configure the access control for CoreSight(master 3 for TRDC2, MDAC_W3). */
+ nonProcAssign.domainId = 0x8U;
+ TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCoreSight, &nonProcAssign);
+ /* Configure the access control for DMA4(master 4 for TRDC2, MDAC_W4). */
+ nonProcAssign.domainId = 0x7U;
+ TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterDMA4, &nonProcAssign);
+ /* Configure the access control for NETC(master 5 for TRDC2, MDAC_W5). */
+ procAssign.domainId = 0xAU;
+ TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterNETC, 0U, &procAssign);
+
+ /* 3. Set the MDAC Configuration in TRDC3. */
+ /* Configure the access control for uSDHC1(master 0 for TRDC3, MDAC_M0). */
+ nonProcAssign.domainId = 0x5U;
+ TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUSDHC1, &nonProcAssign);
+ /* Configure the access control for uSDHC2(master 1 for TRDC3, MDAC_M1). */
+ nonProcAssign.domainId = 0x6U;
+ TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUSDHC2, &nonProcAssign);
+ /* Configure the access control for USB(master 3 for TRDC3, MDAC_M3). */
+ nonProcAssign.domainId = 0xBU;
+ TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUsb, &nonProcAssign);
+ /* Configure the access control for FlexSPI_FLR(master 4 for TRDC3, MDAC_M4). */
+ nonProcAssign.domainId = 0xAU;
+ TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterFlexspiFlr, &nonProcAssign);
+}
+
+static bool TRDC_IsValidDomain(TRDC_Type *trdc, uint8_t domain)
+{
+ bool r = true;
+
+ if ((domain > 11) || (domain < 2) || (domain == 3))
+ {
+ r = false;
+ }
+ return r;
+}
+
+static bool TRDC_IsValidMbc(TRDC_Type *trdc, uint8_t mbc)
+{
+ bool r = false;
+ if (trdc == TRDC1)
+ {
+ switch (mbc)
+ {
+ case 0: /* TRDC1 MBC_A0 */
+ case 1: /* TRDC1 MBC_A1 */
+ r = true;
+ break;
+ default:
+ break;
+ }
+ }
+ else if (trdc == TRDC2)
+ {
+ switch (mbc)
+ {
+ case 0: /* TRDC2 MBC_W0 */
+ case 1: /* TRDC2 MBC_W1 */
+ r = true;
+ break;
+ default:
+ break;
+ }
+ }
+ return r;
+}
+
+static uint32_t TRDC_GetMbcMemNum(TRDC_Type *trdc, uint32_t mbc)
+{
+ uint32_t memNumber = 0U;
+ if (trdc == TRDC1)
+ {
+ uint8_t MemNum[2] = {3, 2};
+ switch (mbc)
+ {
+ case 0: /* TRDC1 MBC_A0 AIPS1/Edgelock/GPIO1 */
+ case 1: /* TRDC1 MBC_A1 CM33 Code-TCM/CM33 System-TCM */
+ memNumber = MemNum[mbc];
+ break;
+ default:
+ break;
+ }
+ }
+ else if (trdc == TRDC2)
+ {
+ uint8_t MemNum[2] = {4, 4};
+ switch (mbc)
+ {
+ case 0: /* TRDC2 MBC_A0 AIPS2/GPIO2, GPIO4, GPIO6/GPIO3, GPIO5/DAP (Debug) */
+ case 1: /* TRDC2 MBC_A1 AIPS3/AHB_ISPAP/NIC_MAIN GPV/SRAMC */
+ memNumber = MemNum[mbc];
+ break;
+ default:
+ break;
+ }
+ }
+ return memNumber;
+}
+
+static bool TRDC_IsValidMbcMem(TRDC_Type *trdc, uint8_t mbc, uint8_t mem)
+{
+ bool r = false;
+ if (trdc == TRDC1)
+ {
+ switch (mbc)
+ {
+ case 0: /* TRDC1 MBC_A0 */
+ switch (mem)
+ {
+ case 0: /* TRDC1 MBC_A0 AIPS1 */
+ r = true;
+ break;
+ case 1: /* TRDC1 MBC_A0 Edgelock */
+ break; /* Intentional, Edgelock region not touched. */
+ case 2: /* TRDC1 MBC_A0 GPIO1 */
+ r = true;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 1: /* TRDC1 MBC_A1 */
+ switch (mem)
+ {
+ case 0: /* TRDC1 MBC_A1 CM33 Code-TCM */
+ case 1: /* TRDC1 MBC_A1 CM33 System-TCM */
+ r = true;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ else if (trdc == TRDC2)
+ {
+ switch (mbc)
+ {
+ case 0: /* TRDC2 MBC_W0 */
+ switch (mem)
+ {
+ case 0: /* TRDC2 MBC_W0 AIPS2 */
+ case 1: /* TRDC2 MBC_W0 GPIO2, GPIO4, GPIO6 */
+ case 2: /* TRDC2 MBC_W0 GPIO3, GPIO5 */
+ case 3: /* TRDC2 MBC_W0 DAP (Debug) */
+ r = true;
+ break;
+
+ default:
+ break;
+ }
+ break;
+ case 1: /* TRDC2 MBC_W1 */
+ switch (mem)
+ {
+ case 0: /* TRDC2 MBC_W1 AIPS3 */
+ case 1: /* TRDC2 MBC_W1 AHB_ISPAP */
+ case 2: /* TRDC2 MBC_W1 NIC_MAIN GPV */
+ case 3: /* TRDC2 MBC_W1 SRAMC */
+ r = true;
+ break;
+
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ return r;
+}
+
+static bool TRDC_IsValidMrc(TRDC_Type *trdc, uint8_t mrc)
+{
+ bool r = false;
+ if (trdc == TRDC1)
+ {
+ switch (mrc)
+ {
+ case 0: /* TRDC1 MRC_A0 */
+ case 1: /* TRDC1 MRC_A1 */
+ r = true;
+ break;
+ default:
+ break;
+ }
+ }
+ else if (trdc == TRDC2)
+ {
+ switch (mrc)
+ {
+ case 1: /* TRDC2 MRC_W1 */
+ case 2: /* TRDC2 MRC_W2 */
+ case 3: /* TRDC2 MRC_W3 */
+ case 4: /* TRDC2 MRC_W4 */
+ case 5: /* TRDC2 MRC_W5 */
+ case 6: /* TRDC2 MRC_W6 */
+ r = true;
+ break;
+ default:
+ break;
+ }
+ }
+ return r;
+}
+
+static bool TRDC_GetMrcRegionAddr(TRDC_Type *trdc, uint8_t mrc, uint32_t *pStartAddr, uint32_t *pStopAddr)
+{
+ bool r = true;
+ if (trdc == TRDC1)
+ {
+ switch (mrc)
+ {
+ case 0: /* TRDC1 MRC_A0 CM33 ROM */
+ *pStartAddr = 0x00000000UL;
+ *pStopAddr = 0x00027FFFUL;
+ break;
+ case 1: /* TRDC1 MRC_A1 FlexSPI2 */
+ *pStartAddr = 0x04000000UL;
+ *pStopAddr = 0x07FFFFFFUL;
+ break;
+ default:
+ r = false;
+ break;
+ }
+ }
+ else if (trdc == TRDC2)
+ {
+ switch (mrc)
+ {
+ case 1: /* TRDC2 MRC_W1 FlexSPI1 */
+ *pStartAddr = 0x28000000UL;
+ *pStopAddr = 0x2FFFFFFFUL;
+ break;
+ case 2: /* TRDC2 MRC_W2 CM7 I-TCM D-TCM */
+ *pStartAddr = 0x203C0000UL;
+ *pStopAddr = 0x2043FFFFUL;
+ break;
+ case 3: /* TRDC2 MRC_W3 OCRAM1 */
+ *pStartAddr = 0x20480000UL;
+ *pStopAddr = 0x204FFFFFUL;
+ break;
+ case 4: /* TRDC2 MRC_W4 OCRAM2 */
+ *pStartAddr = 0x20500000UL;
+ *pStopAddr = 0x2053FFFFUL;
+ break;
+ case 5: /* TRDC2 MRC_W5 SEMC */
+ *pStartAddr = 0x80000000UL;
+ *pStopAddr = 0x8FFFFFFFUL;
+ break;
+ case 6: /* TRDC2 MRC_W6 NETC */
+ *pStartAddr = 0x60000000UL;
+ *pStopAddr = 0x60FFFFFFUL;
+ break;
+ default:
+ r = false;
+ break;
+ }
+ }
+ return r;
+}
+
+void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc)
+{
+ trdc_hardware_config_t hwConfig;
+ trdc_memory_access_control_config_t memAccessConfig;
+ trdc_mbc_memory_block_config_t mbcBlockConfig;
+ trdc_mrc_region_descriptor_config_t mrcRegionConfig;
+
+ TRDC_GetHardwareConfig(trdc, &hwConfig);
+
+ /* Enable all read/write/execute access for MRC/MBC access control. */
+ (void)memset(&memAccessConfig, 0, sizeof(memAccessConfig));
+ memAccessConfig.nonsecureUsrX = 1U;
+ memAccessConfig.nonsecureUsrW = 1U;
+ memAccessConfig.nonsecureUsrR = 1U;
+ memAccessConfig.nonsecurePrivX = 1U;
+ memAccessConfig.nonsecurePrivW = 1U;
+ memAccessConfig.nonsecurePrivR = 1U;
+ memAccessConfig.secureUsrX = 1U;
+ memAccessConfig.secureUsrW = 1U;
+ memAccessConfig.secureUsrR = 1U;
+ memAccessConfig.securePrivX = 1U;
+ memAccessConfig.securePrivW = 1U;
+ memAccessConfig.securePrivR = 1U;
+
+ for (uint32_t mrc = 0U; mrc < hwConfig.mrcNumber; mrc++)
+ {
+ if (TRDC_IsValidMrc(trdc, mrc))
+ {
+ for (uint32_t i = 0U; i < 8U; i++)
+ {
+ TRDC_MrcSetMemoryAccessConfig(trdc, &memAccessConfig, mrc, i);
+ }
+ }
+ }
+
+ for (uint32_t mbc = 0U; mbc < hwConfig.mbcNumber; mbc++)
+ {
+ if (TRDC_IsValidMbc(trdc, mbc))
+ {
+ for (uint32_t i = 0U; i < 8U; i++)
+ {
+ TRDC_MbcSetMemoryAccessConfig(trdc, &memAccessConfig, mbc, i);
+ }
+ }
+ }
+
+ memset(&mbcBlockConfig, 0, sizeof(mbcBlockConfig));
+ mbcBlockConfig.nseEnable = false;
+ mbcBlockConfig.memoryAccessControlSelect = 0;
+
+ memset(&mrcRegionConfig, 0, sizeof(mrcRegionConfig));
+ mrcRegionConfig.memoryAccessControlSelect = 0U;
+ mrcRegionConfig.valid = true;
+ mrcRegionConfig.nseEnable = false;
+ mrcRegionConfig.regionIdx = 0U;
+
+ for (uint32_t domain = 0; domain < hwConfig.domainNumber; domain++)
+ {
+ if (TRDC_IsValidDomain(trdc, domain))
+ {
+ /* Set the configuration for MBC. */
+ for (uint32_t mbc = 0U; mbc < hwConfig.mbcNumber; mbc++)
+ {
+ if (TRDC_IsValidMbc(trdc, mbc))
+ {
+ uint32_t mem_num = TRDC_GetMbcMemNum(trdc, mbc);
+ for (uint32_t mem = 0; mem < mem_num; mem++)
+ {
+ if (TRDC_IsValidMbcMem(trdc, mbc, mem))
+ {
+ trdc_slave_memory_hardware_config_t mbcHwConfig;
+ TRDC_GetMbcHardwareConfig(trdc, &mbcHwConfig, mbc, mem);
+ for (uint32_t block = 0; block < mbcHwConfig.blockNum; block++)
+ {
+ mbcBlockConfig.domainIdx = domain;
+ mbcBlockConfig.mbcIdx = mbc;
+ mbcBlockConfig.slaveMemoryIdx = mem;
+ mbcBlockConfig.memoryBlockIdx = block;
+ TRDC_MbcSetMemoryBlockConfig(trdc, &mbcBlockConfig);
+ }
+ }
+ }
+ }
+ }
+
+ /* Set the configuration for MRC. */
+ for (uint32_t mrc = 0U; mrc < hwConfig.mrcNumber; mrc++)
+ {
+ if (TRDC_IsValidMrc(trdc, mrc))
+ {
+ uint32_t start_addr, end_addr;
+
+ if (TRDC_GetMrcRegionAddr(trdc, mrc, &start_addr, &end_addr))
+ {
+ mrcRegionConfig.startAddr = start_addr;
+ mrcRegionConfig.endAddr = end_addr;
+ mrcRegionConfig.domainIdx = domain;
+ mrcRegionConfig.mrcIdx = mrc;
+ TRDC_MrcSetRegionDescriptorConfig(trdc, &mrcRegionConfig);
+ }
+ else
+ {
+ assert(false);
+ }
+ }
+ }
+ }
+ }
+}
+
+void BOARD_GrantTRDCFullPermissions(void)
+{
+ /* 1. Request TRDC ownership */
+ BOARD_RequestTRDC(true, true, true);
+
+ /* 2. Config DAC. */
+ APP_CommonTrdcDACSetting();
+
+ /* 3. Enable all access control */
+ APP_CommonTrdcAccessControlSetting(TRDC1);
+ APP_CommonTrdcAccessControlSetting(TRDC2);
+}
+
+void BOARD_CommonSetting(void)
+{
+ BOARD_GrantTRDCFullPermissions();
+}
+
/* This is the timer interrupt service routine. */
void SysTick_Handler(void)
{
@@ -271,9 +747,11 @@ void imxrt_uart_pins_init(void)
void rt_hw_board_init()
{
+ BOARD_CommonSetting();
BOARD_ConfigMPU();
BOARD_InitPins();
BOARD_BootClockRUN();
+ BOARD_InitBootPeripherals();
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h
index a69a6880cae..108f6a1cfed 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h
@@ -10,6 +10,7 @@
#include "clock_config.h"
#include "pin_mux.h"
+#include "peripherals.h"
#include "fsl_common.h"
#include "fsl_rgpio.h"
#include "fsl_clock.h"
diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h
index ef905ec6326..91bb4f18dbc 100644
--- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h
+++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h
@@ -106,6 +106,7 @@
#define RT_VER_NUM 0x50300
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
+#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_USING_HW_ATOMIC_8
#define ARCH_USING_HW_ATOMIC_16
@@ -113,7 +114,7 @@
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_FPU
-#define ARCH_ARM_CORTEX_M33
+#define ARCH_ARM_CORTEX_M7
/* RT-Thread Components */
@@ -147,6 +148,8 @@
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_SPI
+#define RT_USING_QSPI
#define RT_USING_PIN
/* end of Device Drivers */
@@ -294,6 +297,10 @@
/* end of Kendryte SDK */
+/* MM32 HAL & SDK Drivers */
+
+/* end of MM32 HAL & SDK Drivers */
+
/* WCH HAL & SDK Drivers */
/* end of WCH HAL & SDK Drivers */
@@ -327,6 +334,10 @@
/* FT32 HAL & SDK Drivers */
/* end of FT32 HAL & SDK Drivers */
+
+/* NOVOSNS Drivers */
+
+/* end of NOVOSNS Drivers */
/* end of HAL & SDK Drivers */
/* sensors drivers */
@@ -418,6 +429,8 @@
#define BSP_USING_LPUART
#define BSP_USING_LPUART1
+#define BSP_USING_FLEXSPI
+#define BSP_USING_FLEXSPI1
/* end of On-chip Peripheral Drivers */
/* Onboard Peripheral Drivers */
diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c
index 0cacdc75f0e..2441dbe7677 100644
--- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c
+++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c
@@ -17,18 +17,15 @@
#include
#endif
-#include "flexspi_port.h"
+#include "ports/flexspi_port.h"
#include "fsl_flexspi.h"
-#define COMBINATION_MODE 1U
-#define FREE_RUNNING_MODE 1U
-
#define FLEXSPI_DEBUG
#define LOG_TAG "drv.flexspi"
#include
-static flexspi_device_config_t deviceconfig = {
- .flexspiRootClk = 12000000,
+flexspi_device_config_t deviceconfig = {
+ .flexspiRootClk = 200000000,
.flashSize = FLASH_SIZE,
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
.CSInterval = 2,
@@ -45,10 +42,54 @@ static flexspi_device_config_t deviceconfig = {
.AHBWriteWaitInterval = 0,
};
-const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
- /* 8bit mode */
- [4 * ARD_SEQ_INDEX] =
- FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
+const uint32_t customLUTOctalMode[CUSTOM_LUT_LENGTH] = {
+
+ /* OPI DDR read */
+ [4 * NOR_CMD_LUT_SEQ_IDX_READ + 0] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC),
+ [4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(
+ kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x20),
+ [4 * NOR_CMD_LUT_SEQ_IDX_READ + 2] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
+
+ /* Read ID */
+ [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F),
+ [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI + 1] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
+
+ /* Write Enable */
+ [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06),
+
+ /* Erase Sector */
+ [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21),
+ [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
+
+ /* Erase Chip */
+ [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xC4, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xC4),
+ [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE + 1] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
+
+ /* Program */
+ [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E),
+ [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
+ kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04),
+
+ /* Dummy write, do nothing when AHB write command is triggered. */
+ [4 * NOR_CMD_LUT_SEQ_IDX_WRITE] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
+
+ /* Read status register using Octal DDR read */
+ [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI] =
+ FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+ [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI + 1] = FLEXSPI_LUT_SEQ(
+ kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
+
};
static void flexspi_clock_init(clock_root_t root, uint8_t src, uint8_t div)
@@ -58,9 +99,17 @@ static void flexspi_clock_init(clock_root_t root, uint8_t src, uint8_t div)
CLOCK_SetRootClockMux(root, src);
}
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address);
+extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, const uint32_t *src);
+extern status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId);
+extern status_t flexspi_nor_enable_octal_mode(FLEXSPI_Type *base);
+extern void flexspi_nor_flash_init(FLEXSPI_Type *base);
+
static int rt_hw_imxrt_flexspi_init(void)
{
- flexspi_config_t config;
FLEXSPI_Type *base;
#ifdef BSP_USING_FLEXSPI1
@@ -69,74 +118,161 @@ static int rt_hw_imxrt_flexspi_init(void)
base = FLEXSPI2_CONTROL_BASE;
#endif
- //Set root clk 80MHz
+ //Set root clk 200MHz
flexspi_clock_init(kCLOCK_Root_Flexspi1, CLOCK_SRC, CLOCK_DIV);
+
+ flexspi_nor_flash_init(base);
+
+ return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_imxrt_flexspi_init);
+
+#ifdef FLEXSPI_DEBUG
+#ifdef FINSH_USING_MSH
+
+#define EXAMPLE_SECTOR 20
+#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI1_AMBA_BASE
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#ifdef BSP_USING_DMA
+AT_NONCACHEABLE_SECTION_ALIGN(static uint8_t s_nor_program_buffer[256], 4);
+#else
+static uint8_t s_nor_program_buffer[256];
+#endif
+static uint8_t s_nor_read_buffer[256];
+
+/* read write hyper flase test */
+static void flexspi_test(void)
+{
+ uint32_t i = 0;
+ status_t status;
+ uint8_t vendorID = 0;
+#ifdef BSP_USING_DMA
+ LOG_W("\r\nFLEXSPI example started! -- DMA mode\r\n");
+#else
+ LOG_W("\r\nFLEXSPI example started!\r\n");
+#endif
+#if defined(FLASH_ENABLE_OCTAL_CMD)
+ /* Enter octal mode unless the FLASH boots in octal mode after reset */
+ status = flexspi_nor_enable_octal_mode(FLEXSPI1_CONTROL_BASE);
+ if (status != kStatus_Success)
+ {
+ #ifdef BSP_USING_DMA
+ LOG_E("Enable octal mode failure ! -- DMA mode\r\n");
+ #else
+ LOG_E("Enable octal mode failure !\r\n");
+ #endif
+ return ;
+ }
+#ifdef BSP_USING_DMA
+ LOG_W("Enabled octal mode. -- DMA mode\r\n");
+#else
+ LOG_W("Enabled octal mode.\r\n");
+#endif
+#endif
- /*Get FLEXSPI default settings and configure the flexspi. */
- FLEXSPI_GetDefaultConfig(&config);
-
- /*Set AHB buffer size for reading data through AHB bus. */
- config.ahbConfig.enableAHBPrefetch = true;
- config.ahbConfig.enableAHBBufferable = true;
- config.ahbConfig.enableReadAddressOpt = true;
- config.ahbConfig.enableAHBCachable = true;
- config.ahbConfig.enableClearAHBBufferOpt = true;
- config.rxSampleClock = FLEXSPI_RX_SAMPLE_CLOCK;
- if(COMBINATION_MODE)
+ /* Get vendor ID. */
+ status = flexspi_nor_get_vendor_id(FLEXSPI1_CONTROL_BASE, &vendorID);
+ if (status != kStatus_Success)
{
- config.enableCombination = true;
+ #ifdef BSP_USING_DMA
+ LOG_E("Get vendor id failure ! -- DMA mode\r\n");
+ #else
+ LOG_E("Get vendor id failure !\r\n");
+ #endif
+ return ;
}
- if(FREE_RUNNING_MODE)
+#ifdef BSP_USING_DMA
+ LOG_W("Vendor ID: 0x%x -- DMA mode\r\n", vendorID);
+ /* Erase sectors. */
+ LOG_W("Erasing Serial NOR over FlexSPI... -- DMA mode\r\n");
+#else
+ LOG_W("Vendor ID: 0x%x\r\n", vendorID);
+ /* Erase sectors. */
+ LOG_W("Erasing Serial NOR over FlexSPI...\r\n");
+#endif
+
+ status = flexspi_nor_flash_erase_sector(FLEXSPI1_CONTROL_BASE, EXAMPLE_SECTOR * SECTOR_SIZE);
+ if (status != kStatus_Success)
{
- config.enableSckFreeRunning = true;
+ #ifdef BSP_USING_DMA
+ LOG_E("Erase sector failure ! -- DMA mode\r\n");
+ #else
+ LOG_E("Erase sector failure !\r\n");
+ #endif
+ return ;
}
- FLEXSPI_Init(base, &config);
- /* Configure flash settings according to serial flash feature. */
- FLEXSPI_SetFlashConfig(base, &deviceconfig, FLASH_PORT);
+#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
+ DCACHE_InvalidateByRange(EXAMPLE_FLEXSPI_AMBA_BASE + EXAMPLE_SECTOR * SECTOR_SIZE, FLASH_PAGE_SIZE);
+#endif
- /* Update LUT table. */
- FLEXSPI_UpdateLUT(base, 0, customLUT, CUSTOM_LUT_LENGTH);
+ memset(s_nor_program_buffer, 0xFFU, sizeof(s_nor_program_buffer));
+ memcpy(s_nor_read_buffer, (void *)(EXAMPLE_FLEXSPI_AMBA_BASE + EXAMPLE_SECTOR * SECTOR_SIZE),
+ sizeof(s_nor_read_buffer));
- /* Do software reset. */
- FLEXSPI_SoftwareReset(base);
+ if (memcmp(s_nor_program_buffer, s_nor_read_buffer, sizeof(s_nor_program_buffer)))
+ {
+ #ifdef BSP_USING_DMA
+ LOG_E("Erase data - read out data value incorrect ! -- DMA mode\r\n ");
+ #else
+ LOG_E("Erase data - read out data value incorrect !\r\n ");
+ #endif
+ return ;
+ }
+ else
+ {
+ #ifdef BSP_USING_DMA
+ LOG_W("Erase data - successfully. -- DMA mode\r\n");
+ #else
+ LOG_W("Erase data - successfully. \r\n");
+ #endif
+ }
- return 0;
-}
-INIT_DEVICE_EXPORT(rt_hw_imxrt_flexspi_init);
+ for (i = 0; i < 0xFFU; i++)
+ {
+ s_nor_program_buffer[i] = i;
+ }
-#ifdef FLEXSPI_DEBUG
-#ifdef FINSH_USING_MSH
+ status =
+ flexspi_nor_flash_page_program(FLEXSPI1_CONTROL_BASE, EXAMPLE_SECTOR * SECTOR_SIZE, (void *)s_nor_program_buffer);
+ if (status != kStatus_Success)
+ {
+ #ifdef BSP_USING_DMA
+ LOG_E("Page program failure ! -- DMA mode\r\n");
+ #else
+ LOG_E("Page program failure !\r\n");
+ #endif
+ return ;
+ }
+
+#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
+ DCACHE_InvalidateByRange(EXAMPLE_FLEXSPI_AMBA_BASE + EXAMPLE_SECTOR * SECTOR_SIZE, FLASH_PAGE_SIZE);
+#endif
-#define FLEXSPI_DATALEN 4U
-static rt_uint32_t send_buf[FLEXSPI_DATALEN] = {0x11223344, 0x55667788, 0x12345678, 0x9900aabb};
-static uint32_t recv_buf[FLEXSPI_DATALEN];
+ memcpy(s_nor_read_buffer, (void *)(EXAMPLE_FLEXSPI_AMBA_BASE + EXAMPLE_SECTOR * SECTOR_SIZE),
+ sizeof(s_nor_read_buffer));
-/* read write 32bit test */
-static void flexspi_test(void)
-{
- volatile rt_uint32_t *flexspi = (rt_uint32_t *)FLEXSPI1_AHB_DATA_ADDRESS; /* FLEXSPI1 start address. */
-
- LOG_D("FLEXSPI Memory 32 bit Write Start\n");
- *(flexspi + 15) = send_buf[3];
- *(flexspi + 8) = send_buf[1];
- *(flexspi + 11) = send_buf[2];
- *(flexspi + 3) = send_buf[0];
- LOG_D("FLEXSPI Memory 32 bit Write End\n");
-
- rt_memset(recv_buf, 0, sizeof(recv_buf));
-
- LOG_D("FLEXSPI Memory 32 bit Read Start\n");
- recv_buf[2] = *(flexspi + 11);
- recv_buf[3] = *(flexspi + 15);
- recv_buf[1] = *(flexspi + 8);
- recv_buf[0] = *(flexspi + 3);
- LOG_D("FLEXSPI Memory 32 bit Read End\n");
-
- LOG_D("addr12 is 0x%x\n", recv_buf[0]);
- LOG_D("addr32 is 0x%x\n", recv_buf[1]);
- LOG_D("addr44 is 0x%x\n", recv_buf[2]);
- LOG_D("addr60 is 0x%x\n", recv_buf[3]);
+ if (memcmp(s_nor_read_buffer, s_nor_program_buffer, sizeof(s_nor_program_buffer)) != 0)
+ {
+ #ifdef BSP_USING_DMA
+ LOG_E("Program data - read out data value incorrect ! -- DMA mode\r\n ");
+ #else
+ LOG_E("Program data - read out data value incorrect !\r\n ");
+ #endif
+ return ;
+ }
+ else
+ {
+ #ifdef BSP_USING_DMA
+ LOG_W("Program data - successfully. -- DMA mode\r\n");
+ #else
+ LOG_W("Program data - successfully. \r\n");
+ #endif
+ }
+
}
MSH_CMD_EXPORT(flexspi_test, flexspi test)