From 4e2043a9a4d35e5028dcbd0cc67e5c4512a76e51 Mon Sep 17 00:00:00 2001 From: "shuta.lst" Date: Tue, 17 Mar 2026 22:36:10 +0800 Subject: [PATCH] feat[bsp][xuantie]: c/r serial cpus support SMP; --- .github/ALL_BSP_COMPILE.json | 4 +- bsp/README.md | 5 +- .../chip_riscv_dummy/gcc_flash_smartl.ld | 21 +- .../include/asm/riscv_asm_macro.h | 60 +- .../chip_riscv_dummy/include/asm/riscv_csr.h | 19 +- .../chip_riscv_dummy/include/csi_config.h | 27 + .../src/arch/{c906fd => c906}/SConscript | 0 .../src/arch/{c906fd => c906}/startup.S | 7 +- .../src/arch/{c906fd => c906}/system.c | 0 .../src/arch/{c906fd => c906}/trap_c.c | 0 .../src/arch/{c906fd => c906}/vectors.S | 0 .../chip_riscv_dummy/src/arch/c907/startup.S | 6 +- .../src/arch/{c908v => c908}/SConscript | 0 .../src/arch/{c908v => c908}/startup.S | 6 +- .../src/arch/{c908v => c908}/system.c | 0 .../src/arch/{c908v => c908}/trap_c.c | 0 .../src/arch/{c908v => c908}/vectors.S | 0 .../chip_riscv_dummy/src/arch/c908x/startup.S | 6 +- .../src/arch/c910v3/startup.S | 191 ----- .../chip_riscv_dummy/src/arch/c910v3/system.c | 324 ------- .../chip_riscv_dummy/src/arch/c910v3/trap_c.c | 64 -- .../src/arch/c910v3/vectors.S | 521 ----------- .../src/arch/{c910v3 => c920v3}/SConscript | 0 .../src/arch/c920v3/startup.S | 5 +- .../src/arch/{e901 => e901plus}/SConscript | 0 .../src/arch/{e901 => e901plus}/startup.S | 4 +- .../src/arch/{e901 => e901plus}/system.c | 0 .../src/arch/{e901 => e901plus}/trap_c.c | 0 .../src/arch/{e901 => e901plus}/vectors.S | 0 .../chip_riscv_dummy/src/arch/e902/startup.S | 70 +- .../chip_riscv_dummy/src/arch/e902/system.c | 17 +- .../chip_riscv_dummy/src/arch/e902/vectors.S | 175 +++- .../chip_riscv_dummy/src/arch/e906/startup.S | 65 +- .../chip_riscv_dummy/src/arch/e906/system.c | 14 +- .../chip_riscv_dummy/src/arch/e906/vectors.S | 489 +++++++++-- .../chip_riscv_dummy/src/arch/e907/startup.S | 65 +- .../chip_riscv_dummy/src/arch/e907/system.c | 12 +- .../chip_riscv_dummy/src/arch/e907/vectors.S | 259 ++++-- .../chip_riscv_dummy/src/arch/r908/startup.S | 4 +- .../chip_riscv_dummy/src/arch/r910/startup.S | 6 +- .../chip_riscv_dummy/src/arch/r920/startup.S | 6 +- .../chip_riscv_dummy/src/sys/feature.c | 86 +- .../chip_riscv_dummy/src/sys/irq_port.c | 38 +- .../chip_riscv_dummy/src/sys/tick.c | 2 - .../csi/csi2/include/core/csi_rv_common.h | 359 ++++++-- .../csi/csi2/include/core/csi_rv_encoding.h | 807 ++++++++++++++++++ .../csi/csi2/include/csi_core.h | 1 + .../xuantie_libraries/lib_cpu/SConscript | 17 + .../xuantie_libraries/lib_cpu/atomic_riscv.c | 159 ++++ .../xuantie_libraries/lib_cpu/clint.c | 350 ++++++++ .../xuantie_libraries/lib_cpu/context_gcc.S | 163 ++++ .../xuantie_libraries/lib_cpu/cpuport.c | 179 ++++ .../xuantie_libraries/lib_cpu/cpuport.h | 111 +++ .../xuantie_libraries/lib_cpu/cpuport_smp.c | 201 +++++ .../xuantie_libraries/lib_cpu/interrupt.c | 94 ++ .../xuantie_libraries/lib_cpu/interrupt_gcc.S | 148 ++++ .../xuantie_libraries/lib_cpu/rt_interrupt.h | 48 ++ .../xuantie_libraries/lib_cpu/stack.h | 88 ++ .../xuantie_libraries/lib_cpu/stackframe.h | 500 +++++++++++ .../xuantie_libraries/pre_main/SConscript | 1 - .../xuantie_libraries/pre_main/libcpu.S | 15 - bsp/xuantie/smartl/e901/board/SConscript | 33 - bsp/xuantie/smartl/{e901 => e901plus}/.config | 45 +- .../smartl/{e901 => e901plus}/.cproject | 18 +- .../smartl/{e901 => e901plus}/.project | 0 .../.settings/org.eclipse.core.runtime.prefs | 0 .../{e901 => e901plus}/.settings/projcfg.ini | 2 +- bsp/xuantie/smartl/{e901 => e901plus}/Kconfig | 2 +- .../smartl/{e901 => e901plus}/README.md | 8 +- .../smartl/{e901 => e901plus}/SConscript | 0 .../smartl/{e901 => e901plus}/SConstruct | 2 +- .../applications/SConscript | 0 .../{e901 => e901plus}/applications/main.c | 0 .../smartl/{e901 => e901plus}/board/Kconfig | 5 - bsp/xuantie/smartl/e901plus/board/SConscript | 15 + .../smartl/{e901 => e901plus}/board/board.c | 0 .../c910 => smartl/e901plus}/board/board.h | 8 +- .../{e901 => e901plus}/figures/1.env.png | Bin .../{e901 => e901plus}/figures/2.scons.png | Bin .../{e901 => e901plus}/figures/3.vscode.png | Bin .../smartl/{e901 => e901plus}/objdump.bat | 2 +- .../smartl/{e901 => e901plus}/qemu.bat | 4 +- .../smartl/{e901 => e901plus}/rtconfig.h | 14 +- .../smartl/{e901 => e901plus}/rtconfig.py | 13 +- .../{e901 => e901plus}/template.cdkproj | 0 .../smartl/{e901 => e901plus}/template.cdkws | 0 .../{e901 => e901plus}/utilities/gdb.init | 0 bsp/xuantie/smartl/e902/.config | 46 +- bsp/xuantie/smartl/e902/README.md | 10 +- bsp/xuantie/smartl/e902/SConstruct | 2 +- bsp/xuantie/smartl/e902/board/Kconfig | 5 - bsp/xuantie/smartl/e902/board/SConscript | 17 +- bsp/xuantie/smartl/e902/board/board.h | 8 +- bsp/xuantie/smartl/e902/rtconfig.h | 11 +- bsp/xuantie/smartl/e902/rtconfig.py | 10 +- bsp/xuantie/smartl/e906/.config | 88 +- bsp/xuantie/smartl/e906/.cproject | 2 +- bsp/xuantie/smartl/e906/Kconfig | 30 + bsp/xuantie/smartl/e906/README.md | 4 +- bsp/xuantie/smartl/e906/SConstruct | 4 +- bsp/xuantie/smartl/e906/board/Kconfig | 19 +- bsp/xuantie/smartl/e906/board/SConscript | 17 +- bsp/xuantie/smartl/e906/board/board.h | 8 +- bsp/xuantie/smartl/e906/qemu.bat | 4 +- bsp/xuantie/smartl/e906/rtconfig.h | 33 +- bsp/xuantie/smartl/e906/rtconfig.py | 14 +- bsp/xuantie/smartl/e906/template.cdkproj | 2 +- bsp/xuantie/smartl/e907/.config | 87 +- bsp/xuantie/smartl/e907/Kconfig | 30 + bsp/xuantie/smartl/e907/README.md | 10 +- bsp/xuantie/smartl/e907/SConstruct | 3 +- bsp/xuantie/smartl/e907/board/Kconfig | 19 +- bsp/xuantie/smartl/e907/board/SConscript | 17 +- bsp/xuantie/smartl/e907/board/board.h | 8 +- bsp/xuantie/smartl/e907/qemu.bat | 4 +- bsp/xuantie/smartl/e907/rtconfig.h | 32 +- bsp/xuantie/smartl/e907/rtconfig.py | 14 +- bsp/xuantie/virt64/c906/libcpu/opcode.h | 2 +- bsp/xuantie/xiaohui/c906/.config | 84 +- bsp/xuantie/xiaohui/c906/Kconfig | 18 +- bsp/xuantie/xiaohui/c906/README.md | 10 +- bsp/xuantie/xiaohui/c906/SConstruct | 2 +- bsp/xuantie/xiaohui/c906/board/Kconfig | 17 - bsp/xuantie/xiaohui/c906/board/SConscript | 26 +- bsp/xuantie/xiaohui/c906/board/board.h | 8 +- bsp/xuantie/xiaohui/c906/rtconfig.h | 29 +- bsp/xuantie/xiaohui/c906/rtconfig.py | 16 +- bsp/xuantie/xiaohui/c907/.config | 97 ++- bsp/xuantie/xiaohui/c907/.cproject | 20 +- bsp/xuantie/xiaohui/c907/Kconfig | 28 +- bsp/xuantie/xiaohui/c907/README.md | 12 +- bsp/xuantie/xiaohui/c907/SConstruct | 2 +- .../xiaohui/c907/applications/SConscript | 3 + bsp/xuantie/xiaohui/c907/applications/main.c | 4 + .../xiaohui/c907/applications/smp_demo.c | 55 ++ bsp/xuantie/xiaohui/c907/board/Kconfig | 19 +- bsp/xuantie/xiaohui/c907/board/SConscript | 26 +- bsp/xuantie/xiaohui/c907/board/board.c | 103 +++ bsp/xuantie/xiaohui/c907/board/board.h | 8 +- bsp/xuantie/xiaohui/c907/qemu.bat | 4 +- bsp/xuantie/xiaohui/c907/rtconfig.h | 38 +- bsp/xuantie/xiaohui/c907/rtconfig.py | 39 +- bsp/xuantie/xiaohui/c907/template.cdkproj | 2 +- bsp/xuantie/xiaohui/c908/.config | 97 ++- bsp/xuantie/xiaohui/c908/Kconfig | 16 + bsp/xuantie/xiaohui/c908/README.md | 12 +- bsp/xuantie/xiaohui/c908/SConstruct | 2 +- .../xiaohui/c908/applications/SConscript | 3 + bsp/xuantie/xiaohui/c908/applications/main.c | 4 + .../xiaohui/c908/applications/smp_demo.c | 55 ++ bsp/xuantie/xiaohui/c908/board/Kconfig | 18 +- bsp/xuantie/xiaohui/c908/board/SConscript | 26 +- bsp/xuantie/xiaohui/c908/board/board.c | 103 +++ bsp/xuantie/xiaohui/c908/board/board.h | 8 +- bsp/xuantie/xiaohui/c908/rtconfig.h | 37 +- bsp/xuantie/xiaohui/c908/rtconfig.py | 37 +- bsp/xuantie/xiaohui/c908x/.config | 88 +- bsp/xuantie/xiaohui/c908x/Kconfig | 5 +- bsp/xuantie/xiaohui/c908x/README.md | 12 +- bsp/xuantie/xiaohui/c908x/SConstruct | 2 +- .../xiaohui/c908x/applications/SConscript | 3 + bsp/xuantie/xiaohui/c908x/applications/main.c | 4 + .../xiaohui/c908x/applications/smp_demo.c | 55 ++ bsp/xuantie/xiaohui/c908x/board/Kconfig | 19 +- bsp/xuantie/xiaohui/c908x/board/SConscript | 26 +- bsp/xuantie/xiaohui/c908x/board/board.c | 103 +++ bsp/xuantie/xiaohui/c908x/board/board.h | 4 +- bsp/xuantie/xiaohui/c908x/rtconfig.h | 30 +- bsp/xuantie/xiaohui/c908x/rtconfig.py | 35 +- bsp/xuantie/xiaohui/c910/board/SConscript | 39 - bsp/xuantie/xiaohui/c910/board/board.c | 41 - bsp/xuantie/xiaohui/{c910 => c920}/.config | 89 +- bsp/xuantie/xiaohui/{c910 => c920}/.cproject | 0 bsp/xuantie/xiaohui/{c910 => c920}/.project | 0 .../.settings/org.eclipse.core.runtime.prefs | 0 .../{c910 => c920}/.settings/projcfg.ini | 2 +- bsp/xuantie/xiaohui/{c910 => c920}/Kconfig | 5 +- bsp/xuantie/xiaohui/{c910 => c920}/README.md | 14 +- bsp/xuantie/xiaohui/{c910 => c920}/SConscript | 0 bsp/xuantie/xiaohui/{c910 => c920}/SConstruct | 2 +- .../{c910 => c920}/applications/SConscript | 3 + .../{c910 => c920}/applications/main.c | 4 + .../xiaohui/c920/applications/smp_demo.c | 55 ++ .../xiaohui/{c910 => c920}/board/Kconfig | 18 +- bsp/xuantie/xiaohui/c920/board/SConscript | 15 + bsp/xuantie/xiaohui/c920/board/board.c | 144 ++++ .../e901 => xiaohui/c920}/board/board.h | 127 ++- .../xiaohui/{c910 => c920}/figures/1.env.png | Bin .../{c910 => c920}/figures/2.scons.png | Bin .../{c910 => c920}/figures/3.vscode.png | Bin .../xiaohui/{c910 => c920}/objdump.bat | 2 +- bsp/xuantie/xiaohui/{c910 => c920}/qemu.bat | 4 +- bsp/xuantie/xiaohui/{c910 => c920}/rtconfig.h | 31 +- .../xiaohui/{c910 => c920}/rtconfig.py | 43 +- .../xiaohui/{c910 => c920}/rtconfig_preinc.h | 0 .../xiaohui/{c910 => c920}/template.cdkproj | 4 +- .../xiaohui/{c910 => c920}/template.cdkws | 0 .../xiaohui/{c910 => c920}/utilities/gdb.init | 0 bsp/xuantie/xiaohui/r908/.config | 95 ++- bsp/xuantie/xiaohui/r908/.cproject | 20 +- bsp/xuantie/xiaohui/r908/Kconfig | 16 + bsp/xuantie/xiaohui/r908/README.md | 12 +- bsp/xuantie/xiaohui/r908/SConstruct | 2 +- .../xiaohui/r908/applications/SConscript | 3 + bsp/xuantie/xiaohui/r908/applications/main.c | 11 +- .../xiaohui/r908/applications/smp_demo.c | 55 ++ bsp/xuantie/xiaohui/r908/board/Kconfig | 18 +- bsp/xuantie/xiaohui/r908/board/SConscript | 26 +- bsp/xuantie/xiaohui/r908/board/board.c | 103 +++ bsp/xuantie/xiaohui/r908/board/board.h | 8 +- bsp/xuantie/xiaohui/r908/qemu.bat | 4 +- bsp/xuantie/xiaohui/r908/rtconfig.h | 36 +- bsp/xuantie/xiaohui/r908/rtconfig.py | 41 +- bsp/xuantie/xiaohui/r910/.config | 85 +- bsp/xuantie/xiaohui/r910/Kconfig | 12 +- bsp/xuantie/xiaohui/r910/README.md | 12 +- bsp/xuantie/xiaohui/r910/SConstruct | 2 +- .../xiaohui/r910/applications/SConscript | 3 + bsp/xuantie/xiaohui/r910/applications/main.c | 4 + .../xiaohui/r910/applications/smp_demo.c | 55 ++ bsp/xuantie/xiaohui/r910/board/Kconfig | 18 +- bsp/xuantie/xiaohui/r910/board/SConscript | 26 +- bsp/xuantie/xiaohui/r910/board/board.c | 103 +++ bsp/xuantie/xiaohui/r910/board/board.h | 8 +- bsp/xuantie/xiaohui/r910/rtconfig.h | 31 +- bsp/xuantie/xiaohui/r910/rtconfig.py | 35 +- bsp/xuantie/xiaohui/r920/.config | 93 +- bsp/xuantie/xiaohui/r920/Kconfig | 18 +- bsp/xuantie/xiaohui/r920/README.md | 12 +- bsp/xuantie/xiaohui/r920/SConstruct | 2 +- .../xiaohui/r920/applications/SConscript | 3 + bsp/xuantie/xiaohui/r920/applications/main.c | 4 + .../xiaohui/r920/applications/smp_demo.c | 55 ++ bsp/xuantie/xiaohui/r920/board/Kconfig | 18 +- bsp/xuantie/xiaohui/r920/board/SConscript | 26 +- bsp/xuantie/xiaohui/r920/board/board.c | 103 +++ bsp/xuantie/xiaohui/r920/board/board.h | 8 +- bsp/xuantie/xiaohui/r920/rtconfig.h | 34 +- bsp/xuantie/xiaohui/r920/rtconfig.py | 37 +- components/finsh/msh.c | 1 + libcpu/Kconfig | 8 + 241 files changed, 7342 insertions(+), 2590 deletions(-) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c906fd => c906}/SConscript (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c906fd => c906}/startup.S (95%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c906fd => c906}/system.c (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c906fd => c906}/trap_c.c (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c906fd => c906}/vectors.S (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c908v => c908}/SConscript (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c908v => c908}/startup.S (97%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c908v => c908}/system.c (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c908v => c908}/trap_c.c (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c908v => c908}/vectors.S (100%) delete mode 100644 bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/startup.S delete mode 100644 bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/system.c delete mode 100644 bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/trap_c.c delete mode 100644 bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/vectors.S rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{c910v3 => c920v3}/SConscript (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{e901 => e901plus}/SConscript (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{e901 => e901plus}/startup.S (99%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{e901 => e901plus}/system.c (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{e901 => e901plus}/trap_c.c (100%) rename bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/{e901 => e901plus}/vectors.S (100%) create mode 100644 bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv_encoding.h create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/SConscript create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/atomic_riscv.c create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/clint.c create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/context_gcc.S create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport.c create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport.h create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport_smp.c create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/interrupt.c create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/interrupt_gcc.S create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/rt_interrupt.h create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/stack.h create mode 100644 bsp/xuantie/libraries/xuantie_libraries/lib_cpu/stackframe.h delete mode 100644 bsp/xuantie/libraries/xuantie_libraries/pre_main/libcpu.S delete mode 100644 bsp/xuantie/smartl/e901/board/SConscript rename bsp/xuantie/smartl/{e901 => e901plus}/.config (97%) rename bsp/xuantie/smartl/{e901 => e901plus}/.cproject (99%) rename bsp/xuantie/smartl/{e901 => e901plus}/.project (100%) rename bsp/xuantie/smartl/{e901 => e901plus}/.settings/org.eclipse.core.runtime.prefs (100%) rename bsp/xuantie/smartl/{e901 => e901plus}/.settings/projcfg.ini (82%) rename bsp/xuantie/smartl/{e901 => e901plus}/Kconfig (90%) rename bsp/xuantie/smartl/{e901 => e901plus}/README.md (98%) rename bsp/xuantie/smartl/{e901 => e901plus}/SConscript (100%) rename bsp/xuantie/smartl/{e901 => e901plus}/SConstruct (96%) rename bsp/xuantie/smartl/{e901 => e901plus}/applications/SConscript (100%) rename bsp/xuantie/smartl/{e901 => e901plus}/applications/main.c (100%) rename bsp/xuantie/smartl/{e901 => e901plus}/board/Kconfig (79%) create mode 100644 bsp/xuantie/smartl/e901plus/board/SConscript rename bsp/xuantie/smartl/{e901 => e901plus}/board/board.c (100%) rename bsp/xuantie/{xiaohui/c910 => smartl/e901plus}/board/board.h (97%) rename bsp/xuantie/smartl/{e901 => e901plus}/figures/1.env.png (100%) rename bsp/xuantie/smartl/{e901 => e901plus}/figures/2.scons.png (100%) rename bsp/xuantie/smartl/{e901 => e901plus}/figures/3.vscode.png (100%) rename bsp/xuantie/smartl/{e901 => e901plus}/objdump.bat (79%) rename bsp/xuantie/smartl/{e901 => e901plus}/qemu.bat (92%) rename bsp/xuantie/smartl/{e901 => e901plus}/rtconfig.h (97%) rename bsp/xuantie/smartl/{e901 => e901plus}/rtconfig.py (87%) rename bsp/xuantie/smartl/{e901 => e901plus}/template.cdkproj (100%) rename bsp/xuantie/smartl/{e901 => e901plus}/template.cdkws (100%) rename bsp/xuantie/smartl/{e901 => e901plus}/utilities/gdb.init (100%) create mode 100644 bsp/xuantie/xiaohui/c907/applications/smp_demo.c create mode 100644 bsp/xuantie/xiaohui/c908/applications/smp_demo.c create mode 100644 bsp/xuantie/xiaohui/c908x/applications/smp_demo.c delete mode 100644 bsp/xuantie/xiaohui/c910/board/SConscript delete mode 100644 bsp/xuantie/xiaohui/c910/board/board.c rename bsp/xuantie/xiaohui/{c910 => c920}/.config (94%) rename bsp/xuantie/xiaohui/{c910 => c920}/.cproject (100%) rename bsp/xuantie/xiaohui/{c910 => c920}/.project (100%) rename bsp/xuantie/xiaohui/{c910 => c920}/.settings/org.eclipse.core.runtime.prefs (100%) rename bsp/xuantie/xiaohui/{c910 => c920}/.settings/projcfg.ini (83%) rename bsp/xuantie/xiaohui/{c910 => c920}/Kconfig (72%) rename bsp/xuantie/xiaohui/{c910 => c920}/README.md (89%) rename bsp/xuantie/xiaohui/{c910 => c920}/SConscript (100%) rename bsp/xuantie/xiaohui/{c910 => c920}/SConstruct (96%) rename bsp/xuantie/xiaohui/{c910 => c920}/applications/SConscript (75%) rename bsp/xuantie/xiaohui/{c910 => c920}/applications/main.c (81%) create mode 100644 bsp/xuantie/xiaohui/c920/applications/smp_demo.c rename bsp/xuantie/xiaohui/{c910 => c920}/board/Kconfig (51%) create mode 100644 bsp/xuantie/xiaohui/c920/board/SConscript create mode 100644 bsp/xuantie/xiaohui/c920/board/board.c rename bsp/xuantie/{smartl/e901 => xiaohui/c920}/board/board.h (77%) rename bsp/xuantie/xiaohui/{c910 => c920}/figures/1.env.png (100%) rename bsp/xuantie/xiaohui/{c910 => c920}/figures/2.scons.png (100%) rename bsp/xuantie/xiaohui/{c910 => c920}/figures/3.vscode.png (100%) rename bsp/xuantie/xiaohui/{c910 => c920}/objdump.bat (79%) rename bsp/xuantie/xiaohui/{c910 => c920}/qemu.bat (92%) rename bsp/xuantie/xiaohui/{c910 => c920}/rtconfig.h (93%) rename bsp/xuantie/xiaohui/{c910 => c920}/rtconfig.py (67%) rename bsp/xuantie/xiaohui/{c910 => c920}/rtconfig_preinc.h (100%) rename bsp/xuantie/xiaohui/{c910 => c920}/template.cdkproj (98%) rename bsp/xuantie/xiaohui/{c910 => c920}/template.cdkws (100%) rename bsp/xuantie/xiaohui/{c910 => c920}/utilities/gdb.init (100%) create mode 100644 bsp/xuantie/xiaohui/r908/applications/smp_demo.c create mode 100644 bsp/xuantie/xiaohui/r910/applications/smp_demo.c create mode 100644 bsp/xuantie/xiaohui/r920/applications/smp_demo.c diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index eeb2c9a4e8f..9977e293f41 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -491,7 +491,7 @@ "RTT_BSP": "xuantie", "RTT_TOOL_CHAIN": "sourcery-Xuantie-900-gcc-elf-newlib", "SUB_RTT_BSP": [ - "xuantie/smartl/e901", + "xuantie/smartl/e901plus", "xuantie/smartl/e902", "xuantie/smartl/e906", "xuantie/smartl/e907", @@ -499,7 +499,7 @@ "xuantie/xiaohui/c907", "xuantie/xiaohui/c908", "xuantie/xiaohui/c908x", - "xuantie/xiaohui/c910", + "xuantie/xiaohui/c920", "xuantie/xiaohui/r908", "xuantie/xiaohui/r910", "xuantie/xiaohui/r920" diff --git a/bsp/README.md b/bsp/README.md index 4f10465b30d..feb1e45c193 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -773,14 +773,15 @@ This document is based on the RT-Thread mainline repository and categorizes the | BSP Name | GPIO | UART | ADC | I2C | SPI | WDT | |----------|------|------|-----|-----|-----|-----| -| [e901](xuantie/smartl/e901) | - | ✅ | - | - | - | - | +| [e901plus](xuantie/smartl/e901plus) | - | ✅ | - | - | - | - | | [e902](xuantie/smartl/e902) | - | ✅ | - | - | - | - | | [e906](xuantie/smartl/e906) | - | ✅ | - | - | - | - | | [e907](xuantie/smartl/e907) | - | ✅ | - | - | - | - | | [c906 (RT-Smart)](xuantie/virt64/c906) | - | ✅ | - | - | - | - | | [c907](xuantie/xiaohui/c907) | - | ✅ | - | - | - | - | | [c908](xuantie/xiaohui/c908) | - | ✅ | - | - | - | - | -| [c910](xuantie/xiaohui/c910) | - | ✅ | - | - | - | - | +| [c908x](xuantie/xiaohui/c908x) | - | ✅ | - | - | - | - | +| [c920](xuantie/xiaohui/c920) | - | ✅ | - | - | - | - | | [r908](xuantie/xiaohui/r908) | - | ✅ | - | - | - | - | | [r910](xuantie/xiaohui/r910) | - | ✅ | - | - | - | - | | [r920](xuantie/xiaohui/r920) | - | ✅ | - | - | - | - | diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl.ld b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl.ld index ac715758b2c..ea4a556e775 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl.ld +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl.ld @@ -24,13 +24,13 @@ ******************************************************************************/ MEMORY { - ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x20000 /* ISRAM 128KB*/ - DSRAM : ORIGIN = 0x20000000 , LENGTH = 0x80000 /* DSRAM 512KB*/ + ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x30000 /* ISRAM 192KB*/ + DSRAM : ORIGIN = 0x20000000 , LENGTH = 0xC0000 /* DSRAM 768KB*/ SRAM : ORIGIN = 0x60000000 , LENGTH = 0x20000 /* SRAM 128KB, no cacheable*/ } __min_heap_size = 0x200; -PROVIDE (__ram_end = 0x20080000); +PROVIDE (__ram_end = 0x200C0000); PROVIDE (__heap_end = __ram_end); REGION_ALIAS("REGION_TEXT", ISRAM); @@ -47,6 +47,7 @@ SECTIONS KEEP(*startup.o(*.text)) KEEP(*startup.o(*.vectors)) KEEP(*vectors.o(*.text)) + KEEP(*whetstone.o(*.text)) KEEP(*(.text.entry)) *(.text*) *(.gnu.warning) @@ -64,6 +65,12 @@ SECTIONS . = ALIGN(0x10) ; __etext = . ; } > REGION_TEXT + .eh_frame_hdr : { + *(.eh_frame_hdr) + } > REGION_TEXT + .eh_frame : ONLY_IF_RO { + KEEP (*(.eh_frame)) + } > REGION_TEXT .rodata : { . = ALIGN(0x4) ; __srodata = .; @@ -189,7 +196,7 @@ SECTIONS KEEP(*(*.post_driver_entry)) __post_driver_end__ = .; /************** end of drivers *********/ - . = ALIGN(0x4) ; + . = ALIGN(0x8) ; __erodata = .; __rodata_end__ = .; } > REGION_RODATA @@ -231,10 +238,10 @@ SECTIONS . = ALIGN(0x4) ; __ram_code_end__ = .; } > REGION_DATA AT > REGION_RODATA - .bss : { - . = ALIGN(0x4) ; - __sbss = ALIGN(0x4) ; + .bss : ALIGN(0x20) { + __sbss = . ; __bss_start__ = . ; + KEEP(*linpack.o(*.bss*)) *(.dynsbss) *(.sbss) *(.sbss.*) diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h index 4eeded81677..4d2de22092b 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h @@ -25,26 +25,14 @@ #ifndef __RISCV_ASM_MACRO_H__ #define __RISCV_ASM_MACRO_H__ -#if (!defined(__riscv_flen)) && (CONFIG_CHECK_FPU_DIRTY) -#error "this cpu doesn't supprot FPU, but macro 'CONFIG_CHECK_FPU_DIRTY' is defined, please remove it." -#endif - -#if (!defined(__riscv_vector)) && (CONFIG_CHECK_VECTOR_DIRTY) -#error "this cpu doesn't supprot vector, but macro 'CONFIG_CHECK_VECTOR_DIRTY' is defined, please remove it." -#endif - -#if (!defined(__riscv_matrix) && !defined(__riscv_xtheadmatrix)) && (CONFIG_CHECK_MATRIX_DIRTY) -#error "this cpu doesn't supprot matrix, but macro 'CONFIG_CHECK_MATRIX_DIRTY' is defined, please remove it." -#endif - +#include #include "riscv_csr.h" -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY .macro RESTORE_MSTATUS /* t0 and t1 are not restored before using */ /* now, sp is at the top of the stack (the lowest address)*/ li t1, 0 -#if __riscv_matrix || __riscv_xtheadmatrix /* matrix registers */ +#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX) /* matrix registers */ #if __riscv_xlen == 64 addi t1, t1, (12 + 12) #else @@ -55,7 +43,7 @@ add t1, t1, t0 #endif /* __riscv_matrix || __riscv_xtheadmatrix */ -#ifdef __riscv_vector /* vector registers */ +#if __riscv_vector && defined(ARCH_RISCV_VECTOR) /* vector registers */ csrr t0, vlenb slli t0, t0, 5 add t1, t1, t0 @@ -66,6 +54,7 @@ #endif /* __riscv_xlen */ #endif /* __riscv_vector */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 /* float registers */ #if __riscv_xlen == 64 addi t1, t1, 168 @@ -76,8 +65,9 @@ #elif __riscv_flen == 32 addi t1, t1, 84 #endif /* __riscv_flen */ +#endif -#ifdef __riscv_dsp /* vxsat register, 32-bit cpu only */ +#if __riscv_dsp && defined(ARCH_RISCV_DSP) /* vxsat register, 32-bit cpu only */ addi t1, t1, 4 #endif /* __riscv_dsp */ @@ -86,19 +76,18 @@ #elif __riscv_xlen == 32 addi t1, t1, 72 #endif - add sp, sp, t1 + add t1, sp, t1 - /* now, sp is the position of mstatus */ - load_x t3, (0)(sp) + /* now, t1 is the position of mstatus */ + load_x t3, (0)(t1) csrw mstatus, t3 - sub sp, sp, t1 .endm .macro RESTORE_SSTATUS /* t0 and t1 are not restored before using */ /* now, sp is at the top of the stack (the lowest address)*/ li t1, 0 -#if __riscv_matrix || __riscv_xtheadmatrix /* matrix registers */ +#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX) /* matrix registers */ #if __riscv_xlen == 64 addi t1, t1, (12 + 12) #else @@ -109,7 +98,7 @@ add t1, t1, t0 #endif /* __riscv_matrix || __riscv_xtheadmatrix */ -#ifdef __riscv_vector /* vector registers */ +#if __riscv_vector && defined(ARCH_RISCV_VECTOR) /* vector registers */ csrr t0, vlenb slli t0, t0, 5 add t1, t1, t0 @@ -120,6 +109,7 @@ #endif /* __riscv_xlen */ #endif /* __riscv_vector */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 /* float registers */ #if __riscv_xlen == 64 addi t1, t1, 168 @@ -130,26 +120,24 @@ #elif __riscv_flen == 32 addi t1, t1, 84 #endif /* __riscv_flen */ +#endif #if __riscv_xlen == 64 /*general purpose registers*/ addi t1, t1, (72 + 72) #elif __riscv_xlen == 32 addi t1, t1, 72 #endif - add sp, sp, t1 + add t1, sp, t1 - /* now, sp is the position of mstatus */ - load_x t3, (0)(sp) + /* now, t1 is the position of mstatus */ + load_x t3, (0)(t1) csrw sstatus, t3 - sub sp, sp, t1 .endm -#endif /* CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY */ - .macro SAVE_VECTOR_REGISTERS /* t0,t1 saved before using */ /* mstatus->t3 */ -#ifdef __riscv_vector +#if __riscv_vector && defined(ARCH_RISCV_VECTOR) #if CONFIG_CHECK_VECTOR_DIRTY /* check if VS filed of MSTATUS is 'dirty' */ li t1, SR_VS_DIRTY @@ -227,7 +215,7 @@ .macro RESTORE_VECTOR_REGISTERS /* t0,t1,t2 not restored before using, mstatus has been restored before using */ -#ifdef __riscv_vector +#if __riscv_vector && defined(ARCH_RISCV_VECTOR) #if CONFIG_CHECK_VECTOR_DIRTY /* check if VS filed of MSTATUS is 'dirty' */ li t1, SR_VS_DIRTY @@ -304,6 +292,7 @@ .macro SAVE_FLOAT_REGISTERS /* t0, t1 saved before using */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 #if CONFIG_CHECK_FPU_DIRTY /* check if FS filed of MSTATUS is 'dirty' */ @@ -378,10 +367,12 @@ fstore_x ft10,72(sp) fstore_x ft11,76(sp) #endif /*__riscv_flen */ +#endif #if CONFIG_CHECK_FPU_DIRTY j 2f 1: /* don't store, move sp only */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 #if __riscv_xlen == 64 addi sp, sp, -168 @@ -391,12 +382,14 @@ #elif __riscv_flen == 32 addi sp, sp, -84 #endif /* __riscv_xlen */ +#endif 2: #endif .endm .macro RESTORE_FLOAT_REGISTERS /* t0 and t1 are not restored before using, mstatus has been restored before using */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 #if CONFIG_CHECK_FPU_DIRTY /* check if FS filed of MSTATUS is 'dirty' */ @@ -472,10 +465,12 @@ fscsr t0 addi sp, sp, 4 #endif /*__riscv_flen */ +#endif #if CONFIG_CHECK_FPU_DIRTY j 2f 1: /* don't restore, move sp only */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 #if __riscv_xlen == 64 addi sp, sp, 168 @@ -485,6 +480,7 @@ #elif __riscv_flen == 32 addi sp, sp, 84 #endif /* __riscv_flen */ +#endif 2: #endif /* CONFIG_CHECK_FPU_DIRTY */ .endm @@ -492,7 +488,7 @@ .macro SAVE_MATRIX_REGISTERS /* t0,t1 saved before using */ -#if __riscv_matrix || __riscv_xtheadmatrix +#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX) #if CONFIG_CHECK_MATRIX_DIRTY /* check if FS filed of MSTATUS is 'dirty' */ li t1, SR_MS_DIRTY @@ -544,7 +540,7 @@ .macro RESTORE_MATRIX_REGISTERS /* t0 and t1 are not restored before using, mstatus has been restored before using */ -#if __riscv_matrix || __riscv_xtheadmatrix +#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX) #if CONFIG_CHECK_MATRIX_DIRTY /* check if FS filed of MSTATUS is 'dirty' */ li t1, SR_MS_DIRTY diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h index 423db93afa2..a6b55d9f499 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h @@ -69,7 +69,9 @@ #define SR_FS_CLEAN 0x00004000UL #define SR_FS_DIRTY 0x00006000UL -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_R920 +#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ + || CONFIG_CPU_XUANTIE_R920 \ + || CONFIG_CPU_XUANTIE_C920 #define SR_VS 0x01800000 #define SR_VS_OFF 0x00000000 #define SR_VS_INITIAL 0x00800000 @@ -128,7 +130,9 @@ #define MSTATUS_MPP_SHIFT 11 #define MSTATUS_MPP (3 << MSTATUS_MPP_SHIFT) -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 +#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ + || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \ + || CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920 #define MSTATUS_VS_SHIFT 23 #else #define MSTATUS_VS_SHIFT 9 @@ -136,9 +140,16 @@ #define MSTATUS_FS_SHIFT 13 #define MSTATUS_MS_SHIFT 25 -#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V ||CONFIG_CPU_XUANTIE_C908I || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 +#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ + || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ + || CONFIG_CPU_XUANTIE_C908_V2 || CONFIG_CPU_XUANTIE_C908V_V2 || CONFIG_CPU_XUANTIE_C908I_V2 \ + || CONFIG_CPU_XUANTIE_C908_CP_V2 || CONFIG_CPU_XUANTIE_C908V_CP_V2 || CONFIG_CPU_XUANTIE_C908I_CP_V2 \ + || CONFIG_CPU_XUANTIE_C908_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908V_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908I_CP_XT_V2 \ + || CONFIG_CPU_XUANTIE_C908VK_CP_V2 || CONFIG_CPU_XUANTIE_C908VK_CP_XT_V2 \ + || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \ + || CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920 #define ATTR_SO (1ull << 4) #define ATTR_CA (1ull << 3) #define ATTR_BU (1ull << 2) diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/csi_config.h b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/csi_config.h index e69de29bb2d..38e1c9baff3 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/csi_config.h +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/csi_config.h @@ -0,0 +1,27 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CSI_CONFIG_H__ +#define __CSI_CONFIG_H__ + +#if CONFIG_KERNEL_RTTHREAD +#include +#endif + + +#endif /* end of __CSI_CONFIG_H__ */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/SConscript similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/SConscript rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/SConscript diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/startup.S similarity index 95% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/startup.S rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/startup.S index e8d56eb6346..adb9e9b8628 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/startup.S @@ -18,10 +18,6 @@ #include -.globl Reset_Handler -.global __rt_rvstack -.equ Mcoret_Handler, SW_handler -.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -56,6 +52,7 @@ __Vectors: .endr .long Reset_Handler _start: + .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: .option push @@ -120,7 +117,7 @@ __exit: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK g_top_irqstack: -__rt_rvstack: + #ifdef CONFIG_KERNEL_NONE .align 4 .global g_base_mainstack diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/system.c similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/system.c rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/system.c diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/trap_c.c similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/trap_c.c rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/trap_c.c diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/vectors.S similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/vectors.S rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/vectors.S diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/startup.S index 43feba91add..07498457995 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/startup.S @@ -22,10 +22,6 @@ #define CONFIG_NR_CPUS 1 #endif -.globl Reset_Handler -.global __rt_rvstack -.equ Mcoret_Handler, SW_handler -.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -65,6 +61,7 @@ __Vectors: .endr .long Reset_Handler _start: + .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: .option push @@ -171,7 +168,6 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: -__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/SConscript similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/SConscript rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/SConscript diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/startup.S similarity index 97% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/startup.S rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/startup.S index 5877d711f25..bad2cb5d718 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/startup.S @@ -22,10 +22,6 @@ #define CONFIG_NR_CPUS 1 #endif -.globl Reset_Handler -.global __rt_rvstack -.equ Mcoret_Handler, SW_handler -.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -65,6 +61,7 @@ __Vectors: .endr .long Reset_Handler _start: + .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: .option push @@ -171,7 +168,6 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: -__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/system.c similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/system.c rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/system.c diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/trap_c.c similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/trap_c.c rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/trap_c.c diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/vectors.S similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/vectors.S rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908/vectors.S diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/startup.S index c5786df51d1..b361b0ce023 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/startup.S @@ -22,10 +22,6 @@ #define CONFIG_NR_CPUS 1 #endif -.globl Reset_Handler -.global __rt_rvstack -.equ Mcoret_Handler, SW_handler -.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -65,6 +61,7 @@ __Vectors: .endr .long Reset_Handler _start: + .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: .option push @@ -180,7 +177,6 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: -__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/startup.S deleted file mode 100644 index 5877d711f25..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/startup.S +++ /dev/null @@ -1,191 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include - -#ifndef CONFIG_NR_CPUS -#define CONFIG_NR_CPUS 1 -#endif - -.globl Reset_Handler -.global __rt_rvstack -.equ Mcoret_Handler, SW_handler -.equ Mirq_Handler, SW_handler -.section .vectors - .align 6 - .globl __Vectors - .type __Vectors, @object -__Vectors: - j Default_Handler /* 0 */ - j Stspend_Handler /* 1 */ - j Default_Handler /* 2 */ - j Mtspend_Handler /* 3 */ - j Default_Handler /* 4 */ - j Scoret_Handler /* 5 */ - j Default_Handler /* 6 */ - j Mcoret_Handler /* 7 */ - j Default_Handler /* 8 */ - j Sirq_Handler /* 9 */ - j Default_Handler /* 10 */ - j Mirq_Handler /* 11 */ - j Default_Handler /* 12 */ - j Default_Handler /* 13 */ - j Default_Handler /* 14 */ - j Default_Handler /* 15 */ -#if CONFIG_ECC_L1_ENABLE - j ECC_L1_Handler /* 16 */ -#else - j Default_Handler /* 16 */ -#endif - - .text - .align 2 - j Reset_Handler - .align 2 - .long 0x594B5343 /* CSKY ASCII */ - .long 0x594B5343 /* CSKY ASCII */ - .align 2 - .rept 9 - .long 0 - .endr - .long Reset_Handler -_start: - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - /* disable ie and clear all interrupts */ - csrw mie, zero - csrw mip, zero - - /* Disable MIE to avoid triggering interrupts before the first task starts. */ - /* This bit is set when a task recovers context. */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrc mstatus, (1 << 1) -#else - csrc mstatus, (1 << 3) -#endif - - la gp, __global_pointer$ -.option pop - la a0, __Vectors - li a1, 0x1 - or a0, a0,a1 - csrw mtvec, a0 - - /* get cpu id */ - csrr a0, mhartid - -#if defined(CONFIG_SMP) && CONFIG_SMP - /* check if hart is within range */ - /* tp: hart id */ - li t0, CONFIG_NR_CPUS - bge a0, t0, hart_out_of_bounds_loop -#endif - -#ifdef CONFIG_KERNEL_NONE - la sp, g_base_mainstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_MAINSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ -#else - la sp, g_base_irqstack - addi t1, a0, 1 - li t2, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t2 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ -#endif - - /* other cpu core, jump to cpu entry directly */ - bnez a0, secondary_cpu_entry - -#ifndef __NO_SYSTEM_INIT - la a0, SystemInit - jalr a0 -#endif - -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - la a0, smode_init - jalr a0 -#endif - -#ifdef CONFIG_KERNEL_NONE - /* Enable interrupt */ -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - csrs sstatus, (1 << 1) -#else - csrs mstatus, (1 << 3) -#endif -#endif - - la a0, rtthread_startup - jalr a0 - -.size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - - .type secondary_cpu_entry, %function -secondary_cpu_entry: -#if defined(CONFIG_SMP) && CONFIG_SMP - la a0, secondary_boot_flag - ld a0, 0(a0) - li a1, 0xa55a - beq a0, a1, 1f -#endif - j secondary_cpu_entry - -#if defined(CONFIG_SMP) && CONFIG_SMP -1: - jal secondary_cpu_c_start - -.size secondary_cpu_entry, . - secondary_cpu_entry - -hart_out_of_bounds_loop: - /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ - wfi - j hart_out_of_bounds_loop -#endif - -.section .stack - .align 4 - .global g_base_irqstack - .global g_top_irqstack -g_base_irqstack: - .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS -g_top_irqstack: -__rt_rvstack: - -#ifdef CONFIG_KERNEL_NONE - .align 4 - .global g_base_mainstack - .global g_top_mainstack -g_base_mainstack: - .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS -g_top_mainstack: -#endif - -#if defined(CONFIG_SMP) && CONFIG_SMP -.data -.global secondary_boot_flag -.align 3 -secondary_boot_flag: - .dword 0 -#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/system.c deleted file mode 100644 index 8157f81729d..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/system.c +++ /dev/null @@ -1,324 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#include -#include "riscv_csr.h" - -#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) -#error "Please check the current system is baremetal or not!!!" -#endif - -#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) -#if CONFIG_NR_CPUS > 1 -#error "Please define CONFIG_NR_CPUS as 1 or do not need define." -#endif -#endif - -#if CONFIG_ECC_L2_ENABLE -static csi_dev_t ecc_l2_dev; -#endif - -extern void section_data_copy(void); -extern void section_ram_code_copy(void); -extern void section_bss_clear(void); - -#ifdef CONFIG_RISCV_SMODE -extern unsigned long __Vectors; -unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); -unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); - -void _mmu_init(void) __attribute__((noinline)); -void _mmu_init(void) -{ -#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ - || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ - || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 - unsigned long status = __get_MXSTATUS(); - /* open MAEE for thead-mmu extension */ - status |= (1 << 21); - __set_MXSTATUS(status); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 - unsigned long envcfgh = __get_MENVCFGH(); - /* enable svpbmt */ - envcfgh |= (1 << 30); - __set_MENVCFGH(envcfgh); - - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ - for (unsigned long i = 1; i < 256; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - for (unsigned long i = 256; i < 512; i++) { - page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } -#else - unsigned long envcfg = __get_MENVCFG(); - /* enable svpbmt */ - envcfg |= (1ull << 62); - __set_MENVCFG(envcfg); - - page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; - page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; - /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ - for (unsigned long i = 0; i < 256; i++) { - page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ - for (unsigned long i = 1; i < 512; i++) { - page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; - } - - /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ - page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; -#endif - -#if __riscv_xlen == 64 - csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); -#endif - csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); - csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); - csi_mmu_invalid_tlb_all(); -#if __riscv_xlen == 64 - __set_SATP(((unsigned long)&page_table_l2 >> 12)); - csi_mmu_set_mode(MMU_MODE_39); - csi_mmu_enable(); -#else - __set_SATP(((unsigned long)&page_table_l1 >> 12)); - csi_mmu_set_mode(MMU_MODE_32); - csi_mmu_enable(); -#endif -} - -void _system_switchto_smode(void) -{ - unsigned long m_status = __get_MSTATUS(); - m_status &= ~MSTATUS_TVM_MASK; - m_status &= ~MSTATUS_MPP_MASK; - m_status |= MSTATUS_MPP_S; - __set_MSTATUS(m_status); - - /* setup S-Mode csr regs */ - __set_STVEC((unsigned long)(&__Vectors) | 0x1); - //FIXME: - __ASM("auipc a0, 0"); - __ASM("addi a0, a0, 14"); - __ASM("csrw mepc, a0"); - __ASM("mret"); -} - -void _system_init_for_smode(void) -{ - _system_switchto_smode(); -} - -void smode_init(void) -{ - /* may be not clear after reset on FPGA */ - csi_mmu_disable(); - _mmu_init(); - _system_init_for_smode(); -} -#endif - -/** - * @brief initialize pmp - * @param None - * @return None - */ -static void pmp_init(void) -{ - long addr; - - addr = 0x90000000UL >> 2; - __set_PMPADDR0(addr); - __set_PMPxCFG(0, 0x8f); -} - -static void interrupt_init(void) -{ - int i; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_PRIO[i] = 31; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_IP[i] = 0; - } - - for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { - PLIC->PLIC_H0_MIE[i] = 0; - PLIC->PLIC_H0_SIE[i] = 0; - } - - /* set hart threshold 0, enable all interrupt */ - PLIC->PLIC_H0_MTH = 0; - PLIC->PLIC_H0_STH = 0; - - for (i = 0; i < CONFIG_IRQ_NUM; i++) { - PLIC->PLIC_H0_MCLAIM = i; - PLIC->PLIC_H0_SCLAIM = i; - } - - /* set PLIC_PER */ - PLIC->PLIC_PER = 0x1; - - /* enable MEIE & MTIE & MSIE */ - uint32_t mie = __get_MIE(); - mie |= (1 << 11 | 1 << 7 | 1 << 3); -#if CONFIG_ECC_L1_ENABLE - mie |= (1 << 16); -#endif - __set_MIE(mie); -} - -static void section_init(void) -{ -#if CONFIG_XIP - section_data_copy(); - section_ram_code_copy(); - csi_dcache_clean(); - csi_icache_invalid(); -#endif - - section_bss_clear(); -} - -static void cache_init(void) -{ - /* enable cache */ - csi_dcache_enable(); - csi_icache_enable(); -} - -/** - * @brief initialize the system - * Initialize the psr and vbr. - * @param None - * @return None - */ -void SystemInit(void) -{ -#if CONFIG_CPU_XUANTIE_C910V3_CP || CONFIG_CPU_XUANTIE_C920V3_CP - /* disable theadisaee & enable MM */ - unsigned long status = __get_MXSTATUS(); - status &= ~(1 << 22); - status |= (1 << 24 | 1 << 15); - __set_MXSTATUS(status); -#else - /* enable theadisaee & MM */ - unsigned long status = __get_MXSTATUS(); - status |= (1 << 22 | 1 << 15); - __set_MXSTATUS(status); -#endif - -#if __riscv_flen == 64 - /* enable float ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_FS_SHIFT); - __set_MSTATUS(status); -#endif -#ifdef __riscv_vector - /* enable vector ISA */ - status = __get_MSTATUS(); - status |= (1 << MSTATUS_VS_SHIFT); - __set_MSTATUS(status); -#endif - -#if CONFIG_ECC_L1_ENABLE - /* enable L1 cache ecc */ - uint64_t mhint = __get_MHINT(); - mhint |= (0x1 << 19); - __set_MHINT(mhint); -#endif - -#if CONFIG_ECC_L2_ENABLE - /* enable L2 cache ecc */ - uint64_t mccr2 = __get_MCCR2(); - mccr2 |= (0x1 << 1); - __set_MCCR2(mccr2); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable ecall delegate */ - unsigned long medeleg = __get_MEDELEG(); - medeleg |= (1 << 9); - __set_MEDELEG(medeleg); - - /* enable interrupt delegate */ - unsigned long mideleg = __get_MIDELEG(); - mideleg |= 0x222; - __set_MIDELEG(mideleg); -#endif - -#ifdef CONFIG_RISCV_SMODE - /* enable mcounteren for s-mode */ - __set_MCOUNTEREN(0xffffffff); - -#if CBO_INSN_SUPPORT - unsigned long envcfg = __get_MENVCFG(); - /* enable CBIE & CBCFE & CBZE on lower priviledge */ - envcfg |= (3 << 4 | 1 << 6 | 1 << 7); - __set_MENVCFG(envcfg); -#endif -#endif - - cache_init(); - section_init(); - pmp_init(); - - interrupt_init(); - soc_set_sys_freq(20000000); - csi_tick_init(); - -#if CONFIG_ECC_L2_ENABLE - extern void ecc_l2_irqhandler(void *arg); - /* l2 cache ecc interrupt register */ - ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; - csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); - csi_irq_enable(ecc_l2_dev.irq_num); -#endif -} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/trap_c.c deleted file mode 100644 index f36e86b2595..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/trap_c.c +++ /dev/null @@ -1,64 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include -#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) -#include -#else -#define printk printf -#endif - -void (*trap_c_callback)(void); - -void trap_c(uintptr_t *regs) -{ - int i; - unsigned long vec = 0; - - vec = __get_MCAUSE(); - - printk("CPU Exception(mcause);: NO.0x%lx", vec); - printk("\n"); - - for (i = 0; i < 31; i++) { - printk("x%d: %p\t", i + 1, (void *)regs[i]); - - if ((i % 4) == 3) { - printk("\n"); - } - } - - printk("\n"); - printk("mepc : %p\n", (void *)regs[31]); - printk("mstatus: %p\n", (void *)regs[32]); - - if (trap_c_callback) { - trap_c_callback(); - } - - while (1); -} - -__attribute__((weak)) void exceptionHandler(void *context) -{ - trap_c((uintptr_t *)context); -} - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/vectors.S deleted file mode 100644 index b49028d1903..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/vectors.S +++ /dev/null @@ -1,521 +0,0 @@ - /* - * Copyright (C) 2017-2024 Alibaba Group Holding Limited - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "riscv_asm_macro.h" - -.section .stack - .align 4 - .global g_trapstackbase - .global g_top_trapstack -g_trapstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK -g_top_trapstack: - -.text -.global _interrupt_return_address - - .align 3 - .weak Scoret_Handler - .type Scoret_Handler, %function -Scoret_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mcoret_Handler - .type Mcoret_Handler, %function -Mcoret_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, CORET_IRQHandler - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - -#if CONFIG_ECC_L1_ENABLE - .align 3 - .weak ECC_L1_Handler - .type ECC_L1_Handler, %function -ECC_L1_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, ECC_L1_IRQHandler - jalr t2 -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret -#endif - - .align 3 - .weak Sirq_Handler - .type Sirq_Handler, %function -Sirq_Handler: - csrw sscratch, sp - la sp, g_top_irqstack - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, sepc - sd t0, (68+68)(sp) - csrr t0, sstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, sstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_SSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw sstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw sepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, sscratch - sret - - - .align 3 - .weak Mirq_Handler - .type Mirq_Handler, %function -Mirq_Handler: - addi sp, sp, -16 - sd t0, (0)(sp) - sd t1, (8)(sp) -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, -8 - sd s0, (sp) -#endif - csrw mscratch, sp - - csrr t0, mhartid - la sp, g_base_irqstack - addi t1, t0, 1 - li t0, CONFIG_ARCH_INTERRUPTSTACK - mul t1, t1, t0 - add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ - - addi sp, sp, -(76+76) - sd t0, (4+4)(sp) - sd t1, (8+8)(sp) - sd t2, (12+12)(sp) - - csrr t0, mepc - sd t0, (68+68)(sp) - csrr t0, mstatus - sd t0, (72+72)(sp) - sd ra, (0 +0 )(sp) - sd a0, (16+16)(sp) - sd a1, (20+20)(sp) - sd a2, (24+24)(sp) - sd a3, (28+28)(sp) - sd a4, (32+32)(sp) - sd a5, (36+36)(sp) - sd a6, (40+40)(sp) - sd a7, (44+44)(sp) - sd t3, (48+48)(sp) - sd t4, (52+52)(sp) - sd t5, (56+56)(sp) - sd t6, (60+60)(sp) - -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - csrr t3, mstatus -#endif - SAVE_FLOAT_REGISTERS - SAVE_VECTOR_REGISTERS - - la t2, do_irq - jalr t2 -_interrupt_return_address: -#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY - RESTORE_MSTATUS -#endif - RESTORE_VECTOR_REGISTERS - RESTORE_FLOAT_REGISTERS - -#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) - ld t0, (72+72)(sp) - csrw mstatus, t0 -#endif - ld t0, (68+68)(sp) - csrw mepc, t0 - - ld ra, (0 +0 )(sp) - ld t0, (4 +4 )(sp) - ld t1, (8 +8 )(sp) - ld t2, (12+12)(sp) - ld a0, (16+16)(sp) - ld a1, (20+20)(sp) - ld a2, (24+24)(sp) - ld a3, (28+28)(sp) - ld a4, (32+32)(sp) - ld a5, (36+36)(sp) - ld a6, (40+40)(sp) - ld a7, (44+44)(sp) - ld t3, (48+48)(sp) - ld t4, (52+52)(sp) - ld t5, (56+56)(sp) - ld t6, (60+60)(sp) - - addi sp, sp, (76+76) - csrr sp, mscratch - -#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP - addi sp, sp, 8 -#endif - ld t0, (0)(sp) - ld t1, (8)(sp) - addi sp, sp, 16 - mret - - -/****************************************************************************** - * Functions: - * void trap(void); - * default exception handler - ******************************************************************************/ - .align 3 - .global trap - .type trap, %function -trap: - csrw mscratch, sp - la sp, g_top_trapstack - addi sp, sp, -(140+140) - sd x1, ( 0 + 0 )(sp) - sd x3, ( 8 + 8 )(sp) - sd x4, ( 12+ 12)(sp) - sd x5, ( 16+ 16)(sp) - sd x6, ( 20+ 20)(sp) - sd x7, ( 24+ 24)(sp) - sd x8, ( 28+ 28)(sp) - sd x9, ( 32+ 32)(sp) - sd x10,( 36+ 36)(sp) - sd x11,( 40+ 40)(sp) - sd x12,( 44+ 44)(sp) - sd x13,( 48+ 48)(sp) - sd x14,( 52+ 52)(sp) - sd x15,( 56+ 56)(sp) - sd x16,( 60+ 60)(sp) - sd x17,( 64+ 64)(sp) - sd x18,( 68+ 68)(sp) - sd x19,( 72+ 72)(sp) - sd x20,( 76+ 76)(sp) - sd x21,( 80+ 80)(sp) - sd x22,( 84+ 84)(sp) - sd x23,( 88+ 88)(sp) - sd x24,( 92+ 92)(sp) - sd x25,( 96+ 96)(sp) - sd x26,(100+100)(sp) - sd x27,(104+104)(sp) - sd x28,(108+108)(sp) - sd x29,(112+112)(sp) - sd x30,(116+116)(sp) - sd x31,(120+120)(sp) - csrr a0, mepc - sd a0, (124+124)(sp) - csrr a0, mstatus - sd a0, (128+128)(sp) - csrr a0, mcause - sd a0, (132+132)(sp) - csrr a0, mtval - sd a0, (136+136)(sp) - csrr a0, mscratch - sd a0, ( 4 + 4 )(sp) - - mv a0, sp - la a1, exceptionHandler - jalr a1 - - .align 3 - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - j trap - - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler Stspend_Handler - def_irq_handler Mtspend_Handler - def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3/SConscript similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/SConscript rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3/SConscript diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3/startup.S index 92ba69989b2..bad2cb5d718 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3/startup.S @@ -22,8 +22,6 @@ #define CONFIG_NR_CPUS 1 #endif -.globl Reset_Handler - .section .vectors .align 6 .globl __Vectors @@ -63,6 +61,7 @@ __Vectors: .endr .long Reset_Handler _start: + .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: .option push @@ -132,7 +131,7 @@ Reset_Handler: #endif #endif - la a0, pre_main + la a0, rtthread_startup jalr a0 .size Reset_Handler, . - Reset_Handler diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/SConscript similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/SConscript rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/SConscript diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/startup.S similarity index 99% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/startup.S rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/startup.S index e22ef51e435..479c73248fb 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/startup.S @@ -17,7 +17,7 @@ */ #include -.global __rt_rvstack + #ifndef CONFIG_SUPPORT_NON_VECTOR_IRQ .section .vectors, "aw", @progbits .align 6 @@ -185,7 +185,7 @@ __exit: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK g_top_irqstack: -__rt_rvstack: + #ifdef CONFIG_KERNEL_NONE .align 3 .global g_base_mainstack diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/system.c similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/system.c rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/system.c diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/trap_c.c similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/trap_c.c rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/trap_c.c diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/vectors.S similarity index 100% rename from bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/vectors.S rename to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901plus/vectors.S diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/startup.S index c5d377905da..e57ee6c9374 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/startup.S @@ -17,7 +17,8 @@ */ #include -.global __rt_rvstack + +#if !CONFIG_SUPPORT_NON_VECTOR_IRQ .section .vectors, "aw", @progbits .align 6 .globl __Vectors @@ -42,7 +43,11 @@ __Vectors: /* External interrupts */ .long Default_IRQHandler +#if CONFIG_IRQ_LATENCY + .long IRQ_LATENCY_IRQHandler +#else .long Default_IRQHandler +#endif .long Default_IRQHandler .long Default_IRQHandler .long Default_IRQHandler @@ -73,8 +78,63 @@ __Vectors: .long Default_IRQHandler .long Default_IRQHandler .long Default_IRQHandler +#else +.section .vectors, "aw", @progbits + .align 6 + .globl __Vectors + .type __Vectors, @object +__Vectors: + .long do_irq + .long do_irq + .long do_irq + .long tspend_handler + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + + /* External interrupts */ + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq +#endif - .globl Reset_Handler .text .align 2 j Reset_Handler @@ -84,7 +144,7 @@ __Vectors: .align 2 _start: .text - .long Reset_Handler + .globl Reset_Handler .align 2 .type Reset_Handler, %function Reset_Handler: @@ -116,14 +176,14 @@ Reset_Handler: __exit: j __exit -.section .stack +.section .stack, "aw", @nobits .align 3 .global g_base_irqstack .global g_top_irqstack g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK g_top_irqstack: -__rt_rvstack: + #ifdef CONFIG_KERNEL_NONE .align 3 .global g_base_mainstack diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/system.c index b4ed4130b52..9de5d64e6ca 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/system.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/system.c @@ -58,17 +58,17 @@ static void clic_init(void) for (i = 0; i < 64; i++) { CLIC->CLICINT[i].IP = 0; +#if !CONFIG_SUPPORT_NON_VECTOR_IRQ CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - csi_vic_set_prio(i, 1); +#else + CLIC->CLICINT[i].ATTR = 0; /* use non-vector interrupt */ +#endif + csi_vic_set_prio(i, 3); } - -#ifndef CONFIG_KERNEL_NONE - /* tspend use lower priority */ - csi_vic_set_prio(Machine_Software_IRQn, 0); - /* tspend use positive interrupt */ + /* tspend use vector&positive interrupt */ CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; + csi_vic_set_prio(Machine_Software_IRQn, 1); csi_irq_enable(Machine_Software_IRQn); -#endif } static void interrupt_init(void) @@ -87,6 +87,9 @@ static void interrupt_init(void) */ void SystemInit(void) { + extern int cpu_features_init(void); + cpu_features_init(); + /* enable theadisaee */ uint32_t status = __get_MXSTATUS(); status |= (1 << 22); diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/vectors.S index 48c6060a86e..7ca7f9c13ed 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/vectors.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e902/vectors.S @@ -18,10 +18,10 @@ #include "riscv_asm_macro.h" -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 +#define RISCV_MCAUSE_IRQ_POS 31 +#define MSTATUS_IEN 8 -.section .stack +.section .stack, "aw", @nobits .align 2 .global g_trapstackbase .global g_top_trapstack @@ -32,11 +32,19 @@ g_top_trapstack: #if CONFIG_SUPPORT_IRQ_NESTED #define IRQ_NESTED_MAX (6) .section .bss -irq_nested_level: -.long 0 + .align 2 + irq_nested_level: + .long 0 -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 + irq_nested_mcause: + .long 0, 0, 0, 0, 0, 0 +#endif + +/* for interrupt tail-chaining debug */ +#if CONFIG_DEBUG_TAIL_CHAINING + .global g_irq_tailchain_loops +g_irq_tailchain_loops: + .long 0 #endif .text @@ -46,18 +54,24 @@ irq_nested_mcause: .weak Default_IRQHandler .type Default_IRQHandler, %function Default_IRQHandler: +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -4 + sw s0, (sp) +#endif csrw mscratch, sp la sp, g_top_irqstack - addi sp, sp, -48 + addi sp, sp, -52 sw t0, 4(sp) sw t1, 8(sp) + sw t2, 12(sp) csrr t0, mepc csrr t1, mcause + csrr t2, mstatus sw t1, 40(sp) sw t0, 44(sp) + sw t2, 48(sp) sw ra, 0(sp) - sw t2, 12(sp) sw a0, 16(sp) sw a1, 20(sp) sw a2, 24(sp) @@ -81,12 +95,12 @@ Default_IRQHandler: and a5, a4, a3 sb a5, 0(a2) - li t0, MSTATUS_PRV1 - csrs mstatus, t0 csrw mcause, a1 lw t0, 44(sp) + lw t1, 48(sp) csrw mepc, t0 + csrw mstatus, t1 lw ra, 0(sp) lw t0, 4(sp) lw t1, 8(sp) @@ -98,12 +112,17 @@ Default_IRQHandler: lw a4, 32(sp) lw a5, 36(sp) - addi sp, sp, 48 + addi sp, sp, 52 csrr sp, mscratch + +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 4 +#endif + mret #else .align 2 - .weak Default_IRQHandler + .weak Default_IRQHandler .type Default_IRQHandler, %function Default_IRQHandler: addi sp, sp, -8 @@ -131,9 +150,12 @@ Default_IRQHandler: li t0, 1 bgt t1, t0, .Lnested1 - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -8 + sw s0, (sp) + csrr t0, mepc + sw t0, 4(sp) +#endif csrw mscratch, sp la sp, g_top_irqstack @@ -143,18 +165,20 @@ Default_IRQHandler: lw t1, 4(sp) addi sp, sp, 8 .Lnested2: - addi sp, sp, -48 + addi sp, sp, -52 sw t0, 4(sp) sw t1, 8(sp) + sw t2, 12(sp) csrr t0, mepc csrr t1, mcause + csrr t2, mstatus sw t1, 40(sp) sw t0, 44(sp) + sw t2, 48(sp) csrs mstatus, 8 sw ra, 0(sp) - sw t2, 12(sp) sw a0, 16(sp) sw a1, 20(sp) sw a2, 24(sp) @@ -167,7 +191,6 @@ Default_IRQHandler: csrc mstatus, 8 - lw a1, 40(sp) andi a0, a1, 0x3FF slli a0, a0, 2 @@ -187,12 +210,12 @@ Default_IRQHandler: sw t1, (t0) bgt t1, zero, .Lnested3 - li t0, MSTATUS_PRV1 - csrs mstatus, t0 csrw mcause, a1 lw t0, 44(sp) + lw t1, 48(sp) csrw mepc, t0 + csrw mstatus, t1 lw ra, 0(sp) lw t0, 4(sp) lw t1, 8(sp) @@ -204,8 +227,14 @@ Default_IRQHandler: lw a4, 32(sp) lw a5, 36(sp) - addi sp, sp, 48 + addi sp, sp, 52 csrr sp, mscratch +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 8 +#endif + lw t0, 0(sp) + lw t1, 4(sp) + addi sp, sp, 8 mret .Lnested3: @@ -220,10 +249,9 @@ Default_IRQHandler: or t0, a0, t0 csrw mcause, t0 lw t0, 44(sp) + lw t1, 48(sp) csrw mepc, t0 - - li t0, MSTATUS_PRV1 - csrs mstatus, t0 + csrw mstatus, t1 lw ra, 0(sp) lw t0, 4(sp) @@ -236,10 +264,12 @@ Default_IRQHandler: lw a4, 32(sp) lw a5, 36(sp) - addi sp, sp, 48 + addi sp, sp, 52 mret #endif + .size Default_IRQHandler, . - Default_IRQHandler + /****************************************************************************** * Functions: * void trap(void); @@ -281,6 +311,7 @@ trap: la a1, exceptionHandler jalr a1 + .size trap, . - trap .align 6 .weak Default_Handler @@ -291,6 +322,10 @@ Default_Handler: sw t0, 0x0(sp) sw t1, 0x4(sp) csrr t0, mcause +#if (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED) + srli t1, t0, RISCV_MCAUSE_IRQ_POS + bnez t1, is_interrupt +#endif andi t0, t0, 0x3FF li t1, 24 beq t0, t1, .NMI_Handler @@ -298,6 +333,82 @@ Default_Handler: lw t1, 0x4(sp) addi sp, sp, 8 j trap +#if (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED) +is_interrupt: + lw t0, 0x0(sp) + lw t1, 0x4(sp) + addi sp, sp, 8 + csrw mscratch, sp + la sp, g_top_irqstack + addi sp, sp, -52 + sw t0, 4(sp) + sw t1, 8(sp) + sw t2, 12(sp) + csrr t0, mepc + csrr t1, mcause + csrr t2, mstatus + sw t1, 40(sp) + sw t0, 44(sp) + sw t2, 48(sp) + + sw ra, 0(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + +#if CONFIG_DEBUG_TAIL_CHAINING + li t2, 0 + la t1, g_irq_tailchain_loops + sw t2, 0(t1) +#endif + + csrrsi t0, mnxti, MSTATUS_IEN + beqz t0, irq_done + +irq_loop: +#if CONFIG_DEBUG_TAIL_CHAINING + la t2, g_irq_tailchain_loops + lw t1, 0(t2) + addi t1, t1, 1 + sw t1, 0(t2) +#endif + lw t1, 0(t0) + jalr t1 + csrrsi t0, mnxti, MSTATUS_IEN + bnez t0, irq_loop + +#if CONFIG_DEBUG_TAIL_CHAINING + li t2, 0 + la a1, g_irq_tailchain_loops + sw t2, 0(a1) +#endif + +irq_done: + lw t0, 40(sp) + lw t1, 44(sp) + lw t2, 48(sp) + csrw mcause, t0 + csrw mepc, t1 + csrw mstatus, t2 + + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + + addi sp, sp, 52 + csrr sp, mscratch + mret +#endif /* (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED) */ .NMI_Handler: /* mscratch may be used before */ addi sp, sp, -4 @@ -306,16 +417,18 @@ Default_Handler: csrw mscratch, sp la sp, g_top_trapstack - addi sp, sp, -48 + addi sp, sp, -52 sw t0, 4(sp) sw t1, 8(sp) + sw t2, 12(sp) csrr t0, mepc csrr t1, mcause + csrr t2, mstatus sw t1, 40(sp) sw t0, 44(sp) + sw t2, 48(sp) sw ra, 0(sp) - sw t2, 12(sp) sw a0, 16(sp) sw a1, 20(sp) sw a2, 24(sp) @@ -339,12 +452,12 @@ Default_Handler: and a5, a4, a3 sb a5, 0(a2) - li t0, MSTATUS_PRV1 - csrs mstatus, t0 csrw mcause, a1 lw t0, 44(sp) + lw t1, 48(sp) csrw mepc, t0 + csrw mstatus, t1 lw ra, 0(sp) lw t0, 4(sp) lw t1, 8(sp) @@ -356,7 +469,7 @@ Default_Handler: lw a4, 32(sp) lw a5, 36(sp) - addi sp, sp, 48 + addi sp, sp, 52 csrr sp, mscratch /* restore mscratch */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/startup.S index 82174509466..136f60d19d4 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/startup.S @@ -18,7 +18,7 @@ #include -.global __rt_rvstack +#if !CONFIG_SUPPORT_NON_VECTOR_IRQ .section .vectors, "aw", @progbits .align 6 .globl __Vectors @@ -106,10 +106,65 @@ __Vectors: .long Default_IRQHandler .long Default_IRQHandler .long Default_IRQHandler +#else /* CONFIG_SUPPORT_NON_VECTOR_IRQ */ +.section .vectors, "aw", @progbits + .align 6 + .globl __Vectors + .type __Vectors, @object +__Vectors: + .long do_irq + .long do_irq + .long do_irq + .long tspend_handler + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + + /* External interrupts */ + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq +#endif /* CONFIG_SUPPORT_NON_VECTOR_IRQ */ .size __Vectors, . - __Vectors - .globl Reset_Handler .text .align 2 j Reset_Handler @@ -119,8 +174,8 @@ __Vectors: .align 2 _start: .text - .long Reset_Handler .align 2 + .global Reset_Handler .type Reset_Handler, %function Reset_Handler: .option push @@ -151,14 +206,14 @@ Reset_Handler: __exit: j __exit -.section .stack +.section .stack, "aw", @nobits .align 4 .global g_base_irqstack .global g_top_irqstack g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK g_top_irqstack: -__rt_rvstack: + #ifdef CONFIG_KERNEL_NONE .align 4 .global g_base_mainstack diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/system.c index 0b8939890d7..4b20c58f374 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/system.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/system.c @@ -60,11 +60,16 @@ static void clic_init(void) for (i = 0; i < 64; i++) { CLIC->CLICINT[i].IP = 0; +#if !CONFIG_SUPPORT_NON_VECTOR_IRQ CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ +#else + CLIC->CLICINT[i].ATTR = 0; /* use non-vector interrupt */ +#endif + csi_vic_set_prio(i, 3); } - - /* tspend use positive interrupt */ + /* tspend use vector&positive interrupt */ CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; + csi_vic_set_prio(Machine_Software_IRQn, 1); csi_irq_enable(Machine_Software_IRQn); } @@ -84,6 +89,9 @@ static void interrupt_init(void) */ void SystemInit(void) { + extern int cpu_features_init(void); + cpu_features_init(); + /* enable theadisaee & MM */ uint32_t status = __get_MXSTATUS(); status |= (1 << 22 | 1 << 15); @@ -107,7 +115,7 @@ void SystemInit(void) cache_init(); section_init(); interrupt_init(); - soc_set_sys_freq(10000000); + soc_set_sys_freq(20000000); csi_tick_init(); } diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/vectors.S index 6bb2e9836c3..6d72ce5a4e4 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/vectors.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/vectors.S @@ -18,10 +18,9 @@ #include "riscv_asm_macro.h" -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 +#define RISCV_MCAUSE_IRQ_POS 31 -.section .stack +.section .stack, "aw", @nobits .align 4 .global g_trapstackbase .global g_top_trapstack @@ -32,11 +31,19 @@ g_top_trapstack: #if CONFIG_SUPPORT_IRQ_NESTED #define IRQ_NESTED_MAX (6) .section .bss -irq_nested_level: -.long 0 + .align 2 + irq_nested_level: + .long 0 + + irq_nested_mcause: + .long 0, 0, 0, 0, 0, 0 +#endif -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 +/* for interrupt tail-chaining debug */ +#if CONFIG_DEBUG_TAIL_CHAINING +.global g_irq_tailchain_loops +g_irq_tailchain_loops: +.long 0 #endif .text @@ -46,23 +53,21 @@ irq_nested_mcause: .weak Default_IRQHandler .type Default_IRQHandler, %function Default_IRQHandler: +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -4 + sw s0, (sp) +#endif csrw mscratch, sp la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif sw t0, 4(sp) sw t1, 8(sp) csrr t0, mepc csrr t1, mcause sw t1, 64(sp) sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif + csrr t1, mstatus + sw t1, 72(sp) sw ra, 0(sp) sw t2, 12(sp) sw a0, 16(sp) @@ -78,14 +83,14 @@ Default_IRQHandler: sw t5, 56(sp) sw t6, 60(sp) -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi sp, sp, -4 csrr t0, vxsat sw t0, 0(sp) #endif /*__riscv_dsp */ #if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus + mv t3, t1 #endif SAVE_FLOAT_REGISTERS @@ -94,13 +99,15 @@ Default_IRQHandler: /* get mcause from sp */ addi t0, sp, 64 -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi t0, t0, 4 #endif /*__riscv_dsp */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 addi t0, t0, 164 #elif __riscv_flen == 32 addi t0, t0, 84 +#endif #endif lw a1, (t0) andi a0, a1, 0x3FF @@ -115,16 +122,13 @@ Default_IRQHandler: and a5, a4, a3 sb a5, 0(a2) -#if CONFIG_CHECK_FPU_DIRTY RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 + csrw mcause, a1 RESTORE_FLOAT_REGISTERS -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) lw t0, 0(sp) csrw vxsat, t0 addi sp, sp, 4 @@ -149,14 +153,15 @@ Default_IRQHandler: lw t5, 56(sp) lw t6, 60(sp) -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif csrr sp, mscratch + +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 4 +#endif + mret -#else +#else /* CONFIG_SUPPORT_IRQ_NESTED */ .align 2 .weak Default_IRQHandler .type Default_IRQHandler, %function @@ -186,9 +191,12 @@ Default_IRQHandler: li t0, 1 bgt t1, t0, .Lnested1 - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -8 + sw s0, (sp) + csrr t0, mepc + sw t0, 4(sp) +#endif csrw mscratch, sp la sp, g_top_irqstack @@ -198,21 +206,16 @@ Default_IRQHandler: lw t1, 4(sp) addi sp, sp, 8 .Lnested2: -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif sw t0, 4(sp) sw t1, 8(sp) csrr t0, mepc csrr t1, mcause sw t1, 64(sp) sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif + csrr t1, mstatus + sw t1, 72(sp) + csrs mstatus, 8 sw ra, 0(sp) @@ -230,14 +233,14 @@ Default_IRQHandler: sw t5, 56(sp) sw t6, 60(sp) -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi sp, sp, -4 csrr t0, vxsat sw t0, 0(sp) #endif /*__riscv_dsp */ #if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus + mv t3, t1 #endif SAVE_FLOAT_REGISTERS @@ -248,13 +251,15 @@ Default_IRQHandler: /* get mcause from sp */ addi t0, sp, 64 -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi t0, t0, 4 #endif /*__riscv_dsp */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 addi t0, t0, 164 #elif __riscv_flen == 32 addi t0, t0, 84 +#endif #endif lw a1, (t0) andi a0, a1, 0x3FF @@ -275,17 +280,13 @@ Default_IRQHandler: sw t1, (t0) bgt t1, zero, .Lnested3 -#if CONFIG_CHECK_FPU_DIRTY RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 csrw mcause, a1 RESTORE_FLOAT_REGISTERS -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) lw t0, 0(sp) csrw vxsat, t0 addi sp, sp, 4 @@ -310,12 +311,14 @@ Default_IRQHandler: lw t5, 56(sp) lw t6, 60(sp) -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif csrr sp, mscratch +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 8 +#endif + lw t0, 0(sp) + lw t1, 4(sp) + addi sp, sp, 8 mret .Lnested3: @@ -330,12 +333,11 @@ Default_IRQHandler: or t0, a0, t0 csrw mcause, t0 -#if CONFIG_CHECK_FPU_DIRTY RESTORE_MSTATUS -#endif + RESTORE_FLOAT_REGISTERS -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) lw t0, 0(sp) csrw vxsat, t0 addi sp, sp, 4 @@ -344,9 +346,6 @@ Default_IRQHandler: lw t0, 68(sp) csrw mepc, t0 - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - lw ra, 0(sp) lw t0, 4(sp) lw t1, 8(sp) @@ -364,13 +363,9 @@ Default_IRQHandler: lw t5, 56(sp) lw t6, 60(sp) -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif mret -#endif +#endif /* CONFIG_SUPPORT_IRQ_NESTED */ /****************************************************************************** * Functions: @@ -429,7 +424,12 @@ trap: la a1, exceptionHandler jalr a1 - +/******************************************************************************* + * Functions: + * void Default_Handler(void); + * Non-Vector Interrupt Handler,Exception Handler,NMI Handler + ******************************************************************************/ +#if !CONFIG_SUPPORT_IRQ_NESTED .align 6 .weak Default_Handler .type Default_Handler, %function @@ -439,13 +439,342 @@ Default_Handler: sw t0, 0x0(sp) sw t1, 0x4(sp) csrr t0, mcause + + srli t1, t0, RISCV_MCAUSE_IRQ_POS + bnez t1, is_interrupt + + andi t0, t0, 0x3FF + li t1, 24 + beq t0, t1, .NMI_Handler + lw t0, 0x0(sp) + lw t1, 0x4(sp) + addi sp, sp, 8 + j trap + +is_interrupt: + lw t0, 0x0(sp) + lw t1, 0x4(sp) + addi sp, sp, 8 +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -4 + sw s0, (sp) +#endif + csrw mscratch, sp + la sp, g_top_irqstack + addi sp, sp, -76 + sw t0, 4(sp) + sw t1, 8(sp) + csrr t0, mepc + csrr t1, mcause + sw t1, 64(sp) + sw t0, 68(sp) + csrr t1, mstatus + sw t1, 72(sp) + + sw ra, 0(sp) + sw t2, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + sw a6, 40(sp) + sw a7, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + +#if __riscv_dsp && defined(ARCH_RISCV_DSP) + addi sp, sp, -4 + csrr t0, vxsat + sw t0, 0(sp) +#endif /*__riscv_dsp */ + +#if CONFIG_CHECK_FPU_DIRTY + mv t3, t1 +#endif + SAVE_FLOAT_REGISTERS + +#if CONFIG_DEBUG_TAIL_CHAINING + li t2, 0 + la t1, g_irq_tailchain_loops + sw t2, 0(t1) +#endif + + csrrci t0, mnxti, MSTATUS_MIE + beqz t0, irq_done + +irq_loop: +#if CONFIG_DEBUG_TAIL_CHAINING + la t2, g_irq_tailchain_loops + lw t1, 0(t2) + addi t1, t1, 1 + sw t1, 0(t2) +#endif + lw t1, 0(t0) + jalr t1 + csrrci t0, mnxti, MSTATUS_MIE + bnez t0, irq_loop + +irq_done: + RESTORE_MSTATUS + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp && defined(ARCH_RISCV_DSP) + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw a1, 64(sp) + csrw mcause, a1 + + lw t0, 68(sp) + csrw mepc, t0 + + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + csrr sp, mscratch + +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 4 +#endif + mret + +#else /* CONFIG_SUPPORT_IRQ_NESTED */ + + .align 6 + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + addi sp, sp, -8 + sw t0, 0x0(sp) + sw t1, 0x4(sp) + + csrr t0, mcause + + /* Check is interrupt */ + srli t1, t0, RISCV_MCAUSE_IRQ_POS + bnez t1, is_interrupt + + /* Check for nmi */ andi t0, t0, 0x3FF li t1, 24 beq t0, t1, .NMI_Handler + lw t0, 0x0(sp) lw t1, 0x4(sp) addi sp, sp, 8 - j trap + + /* is exception */ + j trap + +is_interrupt: + la t0, irq_nested_level + lw t1, (t0) + addi t1, t1, 1 + sw t1, (t0) + + li t0, IRQ_NESTED_MAX + /* nested too deeply, may be error happens */ + bgt t1, t0, trap + + addi t1, t1, -1 + la t0, irq_nested_mcause + slli t1, t1, 2 + add t0, t0, t1 + csrr t1, mcause + sw t1, (t0) + + la t0, irq_nested_level + lw t1, (t0) + li t0, 1 + bgt t1, t0, .Nested_Context + +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -8 + sw s0, (sp) + csrr t0, mepc + sw t0, 4(sp) +#endif + + csrw mscratch, sp + la sp, g_top_irqstack + j .Save_Context + +.Nested_Context: + lw t0, 0(sp) + lw t1, 4(sp) + addi sp, sp, 8 +.Save_Context: + addi sp, sp, -76 + sw t0, 4(sp) + sw t1, 8(sp) + csrr t0, mepc + csrr t1, mcause + sw t1, 64(sp) + sw t0, 68(sp) + csrr t1, mstatus + sw t1, 72(sp) + + sw ra, 0(sp) + sw t2, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + sw a6, 40(sp) + sw a7, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + +#if __riscv_dsp && defined(ARCH_RISCV_DSP) + addi sp, sp, -4 + csrr t0, vxsat + sw t0, 0(sp) +#endif /*__riscv_dsp */ + +#if CONFIG_CHECK_FPU_DIRTY + mv t3, t1 +#endif + SAVE_FLOAT_REGISTERS + + csrrci t0, mnxti, MSTATUS_MIE + csrs mstatus, 8 /* enable irq for preemption */ + lw t1, 0(t0) /* Get handler from vector table */ + jalr t1 /* Call handler */ + + csrc mstatus, 8 /* disable irq for critical section */ + + /* get mcause from sp */ + addi t0, sp, 64 +#if __riscv_dsp && defined(ARCH_RISCV_DSP) + addi t0, t0, 4 +#endif /*__riscv_dsp */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) +#if __riscv_flen == 64 + addi t0, t0, 164 +#elif __riscv_flen == 32 + addi t0, t0, 84 +#endif +#endif + lw a1, (t0) + + la t0, irq_nested_level + lw t1, (t0) + addi t1, t1, -1 + sw t1, (t0) + bgt t1, zero, .Nested_Return + + RESTORE_MSTATUS + + csrw mcause, a1 + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp && defined(ARCH_RISCV_DSP) + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw t0, 68(sp) + csrw mepc, t0 + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + csrr sp, mscratch +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 8 +#endif + lw t0, 0(sp) + lw t1, 4(sp) + addi sp, sp, 8 + mret + +.Nested_Return: + /* keep mpil in current mcause & load exception code before */ + addi t1, t1, -1 + la t0, irq_nested_mcause + slli t1, t1, 2 + add t1, t0, t1 + lw t0, (t1) + andi t0, t0, 0x3FF + andi a0, a1, 0xFFFFFC00 + or t0, a0, t0 + csrw mcause, t0 + + RESTORE_MSTATUS + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp && defined(ARCH_RISCV_DSP) + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw t0, 68(sp) + csrw mepc, t0 + + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + mret +#endif /* CONFIG_SUPPORT_IRQ_NESTED */ .NMI_Handler: /* mscratch may be used before */ addi sp, sp, -4 @@ -454,21 +783,15 @@ Default_Handler: csrw mscratch, sp la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif sw t0, 4(sp) sw t1, 8(sp) csrr t0, mepc csrr t1, mcause sw t1, 64(sp) sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif + csrr t1, mstatus + sw t1, 72(sp) sw ra, 0(sp) sw t2, 12(sp) @@ -485,14 +808,14 @@ Default_Handler: sw t5, 56(sp) sw t6, 60(sp) -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi sp, sp, -4 csrr t0, vxsat sw t0, 0(sp) #endif /*__riscv_dsp */ #if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus + mv t3, t1 #endif SAVE_FLOAT_REGISTERS @@ -501,13 +824,15 @@ Default_Handler: /* get mcause from sp */ addi t0, sp, 64 -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi t0, t0, 4 #endif /*__riscv_dsp */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 addi t0, t0, 164 #elif __riscv_flen == 32 addi t0, t0, 84 +#endif #endif lw a1, (t0) andi a0, a1, 0x3FF @@ -522,16 +847,13 @@ Default_Handler: and a5, a4, a3 sb a5, 0(a2) -#if CONFIG_CHECK_FPU_DIRTY RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 + csrw mcause, a1 RESTORE_FLOAT_REGISTERS -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) lw t0, 0(sp) csrw vxsat, t0 addi sp, sp, 4 @@ -539,10 +861,9 @@ Default_Handler: lw t0, 68(sp) csrw mepc, t0 -#if CONFIG_CHECK_FPU_DIRTY lw t0, 72(sp) csrw mstatus, t0 -#endif + lw ra, 0(sp) lw t0, 4(sp) lw t1, 8(sp) @@ -560,11 +881,7 @@ Default_Handler: lw t5, 56(sp) lw t6, 60(sp) -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif csrr sp, mscratch /* restore mscratch */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/startup.S index 8116bc5f4a1..89c92f5e9d1 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/startup.S @@ -17,7 +17,8 @@ */ #include -.global __rt_rvstack + +#if !CONFIG_SUPPORT_NON_VECTOR_IRQ .section .vectors, "aw", @progbits .align 6 .globl __Vectors @@ -109,10 +110,65 @@ __Vectors: .long Default_IRQHandler .long Default_IRQHandler .long Default_IRQHandler +#else +.section .vectors, "aw", @progbits + .align 6 + .globl __Vectors + .type __Vectors, @object +__Vectors: + .long do_irq + .long do_irq + .long do_irq + .long tspend_handler + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + + /* External interrupts */ + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq + .long do_irq +#endif .size __Vectors, . - __Vectors - .globl Reset_Handler .text .align 2 j Reset_Handler @@ -122,8 +178,8 @@ __Vectors: .align 2 _start: .text - .long Reset_Handler .align 2 + .global Reset_Handler .type Reset_Handler, %function Reset_Handler: .option push @@ -154,14 +210,13 @@ Reset_Handler: __exit: j __exit -.section .stack +.section .stack, "aw", @nobits .align 4 .global g_base_irqstack .global g_top_irqstack g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK g_top_irqstack: -__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 .global g_base_mainstack diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/system.c index 904523c669f..4b20c58f374 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/system.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/system.c @@ -60,11 +60,16 @@ static void clic_init(void) for (i = 0; i < 64; i++) { CLIC->CLICINT[i].IP = 0; +#if !CONFIG_SUPPORT_NON_VECTOR_IRQ CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ +#else + CLIC->CLICINT[i].ATTR = 0; /* use non-vector interrupt */ +#endif + csi_vic_set_prio(i, 3); } - - /* tspend use positive interrupt */ + /* tspend use vector&positive interrupt */ CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3; + csi_vic_set_prio(Machine_Software_IRQn, 1); csi_irq_enable(Machine_Software_IRQn); } @@ -84,6 +89,9 @@ static void interrupt_init(void) */ void SystemInit(void) { + extern int cpu_features_init(void); + cpu_features_init(); + /* enable theadisaee & MM */ uint32_t status = __get_MXSTATUS(); status |= (1 << 22 | 1 << 15); diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/vectors.S index d1f896319f4..a72da34dd3a 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/vectors.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/vectors.S @@ -18,10 +18,10 @@ #include "riscv_asm_macro.h" -/* Enable interrupts when returning from the handler */ -#define MSTATUS_PRV1 0x1880 +#define RISCV_MCAUSE_IRQ_POS 31 +#define MSTATUS_IEN 8 -.section .stack +.section .stack, "aw", @nobits .align 4 .global g_trapstackbase .global g_top_trapstack @@ -32,11 +32,19 @@ g_top_trapstack: #if CONFIG_SUPPORT_IRQ_NESTED #define IRQ_NESTED_MAX (6) .section .bss -irq_nested_level: -.long 0 + .align 2 + irq_nested_level: + .long 0 -irq_nested_mcause: -.long 0, 0, 0, 0, 0, 0 + irq_nested_mcause: + .long 0, 0, 0, 0, 0, 0 +#endif + +/* for interrupt tail-chaining debug */ +#if CONFIG_DEBUG_TAIL_CHAINING +.global g_irq_tailchain_loops +g_irq_tailchain_loops: +.long 0 #endif .text @@ -46,23 +54,21 @@ irq_nested_mcause: .weak Default_IRQHandler .type Default_IRQHandler, %function Default_IRQHandler: +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -4 + sw s0, (sp) +#endif csrw mscratch, sp la sp, g_top_irqstack -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif sw t0, 4(sp) sw t1, 8(sp) csrr t0, mepc csrr t1, mcause sw t1, 64(sp) sw t0, 68(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif + csrr t1, mstatus + sw t1, 72(sp) sw ra, 0(sp) sw t2, 12(sp) sw a0, 16(sp) @@ -78,14 +84,14 @@ Default_IRQHandler: sw t5, 56(sp) sw t6, 60(sp) -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi sp, sp, -4 csrr t0, vxsat sw t0, 0(sp) #endif /*__riscv_dsp */ #if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus + mv t3, t1 #endif SAVE_FLOAT_REGISTERS @@ -94,13 +100,15 @@ Default_IRQHandler: /* get mcause from sp */ addi t0, sp, 64 -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi t0, t0, 4 #endif /*__riscv_dsp */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 addi t0, t0, 164 #elif __riscv_flen == 32 addi t0, t0, 84 +#endif #endif lw a1, (t0) andi a0, a1, 0x3FF @@ -115,16 +123,13 @@ Default_IRQHandler: and a5, a4, a3 sb a5, 0(a2) -#if CONFIG_CHECK_FPU_DIRTY RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 + csrw mcause, a1 RESTORE_FLOAT_REGISTERS -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) lw t0, 0(sp) csrw vxsat, t0 addi sp, sp, 4 @@ -149,12 +154,13 @@ Default_IRQHandler: lw t5, 56(sp) lw t6, 60(sp) -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif csrr sp, mscratch + +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 4 +#endif + mret #else .align 2 @@ -186,9 +192,12 @@ Default_IRQHandler: li t0, 1 bgt t1, t0, .Lnested1 - lw t0, 0(sp) - lw t1, 4(sp) - addi sp, sp, 8 +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -8 + sw s0, (sp) + csrr t0, mepc + sw t0, 4(sp) +#endif csrw mscratch, sp la sp, g_top_irqstack @@ -198,22 +207,16 @@ Default_IRQHandler: lw t1, 4(sp) addi sp, sp, 8 .Lnested2: -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif sw t0, 4(sp) sw t1, 8(sp) csrr t0, mepc csrr t1, mcause sw t1, 64(sp) sw t0, 68(sp) + csrr t1, mstatus + sw t1, 72(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif csrs mstatus, 8 sw ra, 0(sp) @@ -231,14 +234,14 @@ Default_IRQHandler: sw t5, 56(sp) sw t6, 60(sp) -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi sp, sp, -4 csrr t0, vxsat sw t0, 0(sp) #endif /*__riscv_dsp */ #if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus + mv t3, t1 #endif SAVE_FLOAT_REGISTERS @@ -249,13 +252,15 @@ Default_IRQHandler: /* get mcause from sp */ addi t0, sp, 64 -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi t0, t0, 4 #endif /*__riscv_dsp */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 addi t0, t0, 164 #elif __riscv_flen == 32 addi t0, t0, 84 +#endif #endif lw a1, (t0) andi a0, a1, 0x3FF @@ -276,17 +281,13 @@ Default_IRQHandler: sw t1, (t0) bgt t1, zero, .Lnested3 -#if CONFIG_CHECK_FPU_DIRTY RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 csrw mcause, a1 RESTORE_FLOAT_REGISTERS -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) lw t0, 0(sp) csrw vxsat, t0 addi sp, sp, 4 @@ -311,12 +312,14 @@ Default_IRQHandler: lw t5, 56(sp) lw t6, 60(sp) -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif csrr sp, mscratch +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 8 +#endif + lw t0, 0(sp) + lw t1, 4(sp) + addi sp, sp, 8 mret .Lnested3: @@ -331,12 +334,11 @@ Default_IRQHandler: or t0, a0, t0 csrw mcause, t0 -#if CONFIG_CHECK_FPU_DIRTY RESTORE_MSTATUS -#endif + RESTORE_FLOAT_REGISTERS -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) lw t0, 0(sp) csrw vxsat, t0 addi sp, sp, 4 @@ -345,9 +347,6 @@ Default_IRQHandler: lw t0, 68(sp) csrw mepc, t0 - li t0, MSTATUS_PRV1 - csrs mstatus, t0 - lw ra, 0(sp) lw t0, 4(sp) lw t1, 8(sp) @@ -365,11 +364,7 @@ Default_IRQHandler: lw t5, 56(sp) lw t6, 60(sp) -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif mret #endif @@ -440,6 +435,10 @@ Default_Handler: sw t0, 0x0(sp) sw t1, 0x4(sp) csrr t0, mcause +#if (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED) + srli t1, t0, RISCV_MCAUSE_IRQ_POS + bnez t1, is_interrupt +#endif andi t0, t0, 0x3FF li t1, 24 beq t0, t1, .NMI_Handler @@ -447,6 +446,114 @@ Default_Handler: lw t1, 0x4(sp) addi sp, sp, 8 j trap +#if (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED) +is_interrupt: + lw t0, 0x0(sp) + lw t1, 0x4(sp) + addi sp, sp, 8 + csrw mscratch, sp + la sp, g_top_irqstack + addi sp, sp, -76 + sw t0, 4(sp) + sw t1, 8(sp) + csrr t0, mepc + csrr t1, mcause + sw t1, 64(sp) + sw t0, 68(sp) + csrr t1, mstatus + sw t1, 72(sp) + + sw ra, 0(sp) + sw t2, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw a4, 32(sp) + sw a5, 36(sp) + sw a6, 40(sp) + sw a7, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + +#if __riscv_dsp && defined(ARCH_RISCV_DSP) + addi sp, sp, -4 + csrr t0, vxsat + sw t0, 0(sp) +#endif /*__riscv_dsp */ + +#if CONFIG_CHECK_FPU_DIRTY + mv t3, t1 +#endif + SAVE_FLOAT_REGISTERS + +#if CONFIG_DEBUG_TAIL_CHAINING + li t2, 0 + la t1, g_irq_tailchain_loops + sw t2, 0(t1) +#endif + + csrrsi t0, mnxti, MSTATUS_IEN + beqz t0, irq_done + +irq_loop: +#if CONFIG_DEBUG_TAIL_CHAINING + la t2, g_irq_tailchain_loops + lw t1, 0(t2) + addi t1, t1, 1 + sw t1, 0(t2) +#endif + lw t1, 0(t0) + jalr t1 + csrrsi t0, mnxti, MSTATUS_IEN + bnez t0, irq_loop + +#if CONFIG_DEBUG_TAIL_CHAINING + li t2, 0 + la a1, g_irq_tailchain_loops + sw t2, 0(a1) +#endif + +irq_done: + RESTORE_MSTATUS + + RESTORE_FLOAT_REGISTERS + +#if __riscv_dsp && defined(ARCH_RISCV_DSP) + lw t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, 4 +#endif /*__riscv_dsp */ + + lw a1, 64(sp) + csrw mcause, a1 + + lw t0, 68(sp) + csrw mepc, t0 + + lw ra, 0(sp) + lw t0, 4(sp) + lw t1, 8(sp) + lw t2, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw a4, 32(sp) + lw a5, 36(sp) + lw a6, 40(sp) + lw a7, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + + addi sp, sp, 76 + csrr sp, mscratch + mret +#endif /* (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED) */ .NMI_Handler: /* mscratch may be used before */ addi sp, sp, -4 @@ -455,22 +562,16 @@ Default_Handler: csrw mscratch, sp la sp, g_top_trapstack -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, -76 -#else - addi sp, sp, -72 -#endif sw t0, 4(sp) sw t1, 8(sp) csrr t0, mepc csrr t1, mcause sw t1, 64(sp) sw t0, 68(sp) + csrr t1, mstatus + sw t1, 72(sp) -#if CONFIG_CHECK_FPU_DIRTY - csrr t0, mstatus - sw t0, 72(sp) -#endif sw ra, 0(sp) sw t2, 12(sp) sw a0, 16(sp) @@ -486,14 +587,14 @@ Default_Handler: sw t5, 56(sp) sw t6, 60(sp) -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi sp, sp, -4 csrr t0, vxsat sw t0, 0(sp) #endif /*__riscv_dsp */ #if CONFIG_CHECK_FPU_DIRTY - csrr t3, mstatus + mv t3, t1 #endif SAVE_FLOAT_REGISTERS @@ -502,13 +603,15 @@ Default_Handler: /* get mcause from sp */ addi t0, sp, 64 -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) addi t0, t0, 4 #endif /*__riscv_dsp */ +#if __riscv_flen && defined(ARCH_RISCV_FPU) #if __riscv_flen == 64 addi t0, t0, 164 #elif __riscv_flen == 32 addi t0, t0, 84 +#endif #endif lw a1, (t0) andi a0, a1, 0x3FF @@ -523,16 +626,13 @@ Default_Handler: and a5, a4, a3 sb a5, 0(a2) -#if CONFIG_CHECK_FPU_DIRTY RESTORE_MSTATUS -#endif - li t0, MSTATUS_PRV1 - csrs mstatus, t0 + csrw mcause, a1 RESTORE_FLOAT_REGISTERS -#if __riscv_dsp +#if __riscv_dsp && defined(ARCH_RISCV_DSP) lw t0, 0(sp) csrw vxsat, t0 addi sp, sp, 4 @@ -540,6 +640,9 @@ Default_Handler: lw t0, 68(sp) csrw mepc, t0 + lw t0, 72(sp) + csrw mstatus, t0 + lw ra, 0(sp) lw t0, 4(sp) lw t1, 8(sp) @@ -557,11 +660,7 @@ Default_Handler: lw t5, 56(sp) lw t6, 60(sp) -#if CONFIG_CHECK_FPU_DIRTY addi sp, sp, 76 -#else - addi sp, sp, 72 -#endif csrr sp, mscratch /* restore mscratch */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/startup.S index 14c3bf68ccf..7a7c38825d5 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/startup.S @@ -21,8 +21,6 @@ #ifndef CONFIG_NR_CPUS #define CONFIG_NR_CPUS 1 #endif -.global __rt_rvstack -.globl Reset_Handler .section .vectors .align 6 @@ -158,6 +156,7 @@ __Vectors: .endr .long Reset_Handler _start: + .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: .option push @@ -273,7 +272,6 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: -__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/startup.S index 5877d711f25..bad2cb5d718 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/startup.S @@ -22,10 +22,6 @@ #define CONFIG_NR_CPUS 1 #endif -.globl Reset_Handler -.global __rt_rvstack -.equ Mcoret_Handler, SW_handler -.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -65,6 +61,7 @@ __Vectors: .endr .long Reset_Handler _start: + .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: .option push @@ -171,7 +168,6 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: -__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/startup.S index 5877d711f25..bad2cb5d718 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/startup.S +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/startup.S @@ -22,10 +22,6 @@ #define CONFIG_NR_CPUS 1 #endif -.globl Reset_Handler -.global __rt_rvstack -.equ Mcoret_Handler, SW_handler -.equ Mirq_Handler, SW_handler .section .vectors .align 6 .globl __Vectors @@ -65,6 +61,7 @@ __Vectors: .endr .long Reset_Handler _start: + .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: .option push @@ -171,7 +168,6 @@ hart_out_of_bounds_loop: g_base_irqstack: .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS g_top_irqstack: -__rt_rvstack: #ifdef CONFIG_KERNEL_NONE .align 4 diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/feature.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/feature.c index bb505316466..ff41330f90a 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/feature.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/feature.c @@ -18,7 +18,7 @@ #include -/* I/D Cache will enable in cache_init */ +// I/D Cache will enable in cache_init void cpu_features_init(void) { #if CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP @@ -29,7 +29,7 @@ void cpu_features_init(void) return; #endif -#if CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT +#if CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M return; #endif @@ -51,8 +51,7 @@ void cpu_features_init(void) /* As CPUID is a fifo register, try to find * the CPUID[0] whose index(bit[31:28]) == 0 */ - for (i = 0; i < 8; i++) - { + for (i = 0; i < 8; i++) { version[0] = rv_csr_read(CSR_MCPUID); if (((version[0]&0xf0000000) >> 28) == 0) break; @@ -62,8 +61,8 @@ void cpu_features_init(void) version[i] = rv_csr_read(CSR_MCPUID); cpu_type = (version[0] >> 18) & 0xf; - cpu_tnmodel = (version[0] >> 14) & 0x1; - cpu_ver = (version[1] >> 12) & 0xffff; + cpu_tnmodel = (version[0] >> 14) & 0x1; + cpu_ver = (version[1] >> 12) & 0xffff; rv_csr_write(CSR_MCOR, 0x70013); @@ -71,11 +70,9 @@ void cpu_features_init(void) * Warning: CSR_MCCR2 contains an L2 cache latency setting, * you need to confirm it by your own soc design. */ - switch (cpu_type) - { + switch (cpu_type) { case 0x1: - if (cpu_ver >= 0x0) - { + if (cpu_ver >= 0x0) { rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe249000b); rv_csr_write(CSR_MXSTATUS, 0x638000); @@ -87,8 +84,7 @@ void cpu_features_init(void) } break; case 0x2: - if (cpu_ver >= 0x0) - { + if (cpu_ver >= 0x0) { rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xa042000a); rv_csr_write(CSR_MXSTATUS, 0x438100); @@ -103,14 +99,12 @@ void cpu_features_init(void) } break; case 0x3: - if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf) - { /* 1.2.0~1.2.x */ + if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf) { //1.2.0~1.2.x rv_csr_write(CSR_MCCR2, 0xe0010009); rv_csr_write(CSR_MXSTATUS, 0x638000); rv_csr_write(CSR_MHINT, 0x6e30c); rv_csr_write(CSR_MHCR, 0x1ff & (~0x3)); - } else if (cpu_ver == 0x10ca) - { /* 1.3.10 */ + } else if (cpu_ver == 0x10ca) { //1.3.10 rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe2490009); rv_csr_write(CSR_MXSTATUS, 0x638000); @@ -118,39 +112,34 @@ void cpu_features_init(void) rv_csr_write(CSR_MHCR, 0x17f & (~0x3)); rv_csr_write(CSR_MHINT2, 0x420000); rv_csr_write(CSR_MHINT4, 0x410); - } else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f) - { /* 1.4.0~1.4.x */ + } else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f) { //1.4.0~1.4.x rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe2490009); rv_csr_write(CSR_MXSTATUS, 0x638000); rv_csr_write(CSR_MHINT, 0x16e30c); rv_csr_write(CSR_MHCR, 0x1ff & (~0x3)); - } else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f) - { /* 1.5.0~1.5.x */ + } else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f) { //1.5.0~1.5.x rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe2490009); rv_csr_write(CSR_MXSTATUS, 0x638000); rv_csr_write(CSR_MHINT, 0xe6e30c); rv_csr_write(CSR_MHINT2, 0x180); rv_csr_write(CSR_MHCR, 0x1ff & (~0x3)); - } else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183) - { /* 1.6.0~1.6.3 */ + } else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183) { //1.6.0~1.6.3 rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe249000b); rv_csr_write(CSR_MXSTATUS, 0x638000); rv_csr_write(CSR_MHINT, 0x1ee30c); rv_csr_write(CSR_MHINT2, 0x180); rv_csr_write(CSR_MHCR, 0x1ff & (~0x3)); - } else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f) - { /* 1.6.4~1.8.x */ + } else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f) { //1.6.4~1.8.x rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe249000b); rv_csr_write(CSR_MXSTATUS, 0x638000); rv_csr_write(CSR_MHINT, 0x1ee30c); rv_csr_write(CSR_MHINT2, 0x180); rv_csr_write(CSR_MHCR, 0x11ff & (~0x3)); - } else if (cpu_ver >= 0x2000 && cpu_ver <= 0x200e) - { /* 2.0.0~2.0.14 */ + } else if (cpu_ver >= 0x2000 && cpu_ver <= 0x200e) { //2.0.0~2.0.14 rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe249000b); rv_csr_write(CSR_MXSTATUS, 0x438000); @@ -160,8 +149,7 @@ void cpu_features_init(void) #if __riscv_xlen == 64 rv_csr_write(CSR_MENVCFG, 0x4000000000000000); #endif - } else if (cpu_ver >= 0x200f && cpu_ver <= 0x2045) - { /* 2.0.15~2.1.5 */ + } else if (cpu_ver >= 0x200f && cpu_ver <= 0x2045) { //2.0.15~2.1.5 rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe249000b); rv_csr_write(CSR_MXSTATUS, 0x438000); @@ -171,8 +159,7 @@ void cpu_features_init(void) #if __riscv_xlen == 64 rv_csr_write(CSR_MENVCFG, 0x4000000000000000); #endif - } else if (cpu_ver >= 0x2046 && cpu_ver <= 0x20c3) - { /* 2.1.6~2.3.3 */ + } else if (cpu_ver >= 0x2046 && cpu_ver <= 0x20c3) { //2.1.6~2.3.3 rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe249000b); rv_csr_write(CSR_MXSTATUS, 0x438000); @@ -182,8 +169,7 @@ void cpu_features_init(void) #if __riscv_xlen == 64 rv_csr_write(CSR_MENVCFG, 0x4000000000000000); #endif - } else if (cpu_ver >= 0x20c4 && cpu_ver <= 0x2fff) - { /* 2.3.4~2.x.x */ + } else if (cpu_ver >= 0x20c4 && cpu_ver <= 0x2fff) { //2.3.4~2.x.x rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe249000b); rv_csr_write(CSR_MXSTATUS, 0x438100); @@ -194,8 +180,7 @@ void cpu_features_init(void) #if __riscv_xlen == 64 rv_csr_write(CSR_MENVCFG, 0x4000000000000000); #endif - } else if (cpu_ver >= 0x3000 && cpu_ver <= 0x3fff) - { /* 3.0.0~3.x.x */ + } else if (cpu_ver >= 0x3000 && cpu_ver <= 0x3fff) { //3.0.0~3.x.x rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe249000b); rv_csr_write(CSR_MXSTATUS, 0x438100); @@ -211,8 +196,7 @@ void cpu_features_init(void) } break; case 0x4: - if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff) - { + if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff) { rv_csr_write(CSR_MHCR, 0x17f & (~0x3)); rv_csr_write(CSR_MXSTATUS, 0x638000); rv_csr_write(CSR_MHINT, 0x650c); @@ -221,17 +205,14 @@ void cpu_features_init(void) } break; case 0x5: - if(cpu_tnmodel == 0) - { /* c908 */ - if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007) - { /* 0.0.0~0.0.7 */ + if(cpu_tnmodel == 0) { //c908 + if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007) { //0.0.0~0.0.7 rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xe0420008); rv_csr_write(CSR_MXSTATUS, 0x638000); rv_csr_write(CSR_MHINT, 0x2c50c); rv_csr_write(CSR_MHCR, 0x11ff & (~0x3)); - } else if (cpu_ver >= 0x0040 && cpu_ver <= 0x1002) - { /* 0.1.0~1.0.2 */ + } else if (cpu_ver >= 0x0040 && cpu_ver <= 0x1002) { //0.1.0~1.0.2 rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xa042000a); rv_csr_write(CSR_MXSTATUS, 0x438000); @@ -240,8 +221,7 @@ void cpu_features_init(void) #if __riscv_xlen == 64 rv_csr_write(CSR_MENVCFG, 0x4000000000000000); #endif - } else if (cpu_ver >= 0x1003 && cpu_ver <= 0x100b) - { /* 1.0.3~1.0.11 */ + } else if (cpu_ver >= 0x1003 && cpu_ver <= 0x100b) { //1.0.3~1.0.11 rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xa042000a); @@ -251,8 +231,7 @@ void cpu_features_init(void) #if __riscv_xlen == 64 rv_csr_write(CSR_MENVCFG, 0x4000000000000000); #endif - } else if (cpu_ver >= 0x100c && cpu_ver <= 0x1fff) - { /* 1.0.12~ */ + } else if (cpu_ver >= 0x100c && cpu_ver <= 0x1fff) { //1.0.12~ rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xa042000a); rv_csr_write(CSR_MXSTATUS, 0x438100); @@ -262,8 +241,7 @@ void cpu_features_init(void) #if __riscv_xlen == 64 rv_csr_write(CSR_MENVCFG, 0x4000000000000000); #endif - } else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff) - { /* 2.0.0~ */ + } else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff) { //2.0.0~ rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xa042000a); rv_csr_write(CSR_MXSTATUS, 0x438100); @@ -276,10 +254,8 @@ void cpu_features_init(void) } else { while(1); } - } else if (cpu_tnmodel == 1) - { - if (cpu_ver >= 0x0) - { + } else if (cpu_tnmodel == 1) { + if (cpu_ver >= 0x0) { rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xA0420002); rv_csr_write(CSR_MXSTATUS, 0x438100); @@ -297,8 +273,7 @@ void cpu_features_init(void) } break; case 0x6: - if (cpu_ver >= 0x0) - { + if (cpu_ver >= 0x0) { rv_csr_write(CSR_MSMPR, 0x1); rv_csr_write(CSR_MCCR2, 0xA0420002); rv_csr_write(CSR_MXSTATUS, 0x438000); @@ -312,8 +287,7 @@ void cpu_features_init(void) } break; default: - /* FIXME: maybe qemu */ + // FIXME: maybe qemu break; } } - diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/irq_port.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/irq_port.c index 7fa2ae9a0ee..190a884c9b9 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/irq_port.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/irq_port.c @@ -55,27 +55,39 @@ void soc_irq_priority(uint32_t irq_num, uint32_t priority) */ uint32_t soc_irq_get_irq_num(void) { -#if CONFIG_CPU_XUANTIE_E9XX - return (__get_MCAUSE() & 0x3FFU); + int hartid = csi_get_cpu_id(); +#if CONFIG_INTC_CLIC || CONFIG_CPU_XUANTIE_E9XX + (void) hartid; +#if CONFIG_RISCV_SMODE + return (__get_SCAUSE() & 0x3FFU); #else + return (__get_MCAUSE() & 0x3FFU); +#endif /* CONFIG_RISCV_SMODE */ +#endif /* CONFIG_INTC_CLIC */ + +#if CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC uint32_t num; -#if CONFIG_INTC_CLIC_PLIC +#if CONFIG_RISCV_SMODE + uint32_t irqn = __get_SCAUSE() & 0x3FFU; +#else uint32_t irqn = __get_MCAUSE() & 0x3FFU; - if (irqn == Machine_External_IRQn) { - num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_MCLAIM, csi_get_cpu_id()); +#endif /* CONFIG_RISCV_SMODE */ + if (irqn == Machine_External_IRQn || irqn == Supervisor_External_IRQn) { +#if CONFIG_RISCV_SMODE + num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_SCLAIM, hartid); +#else + num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_MCLAIM, hartid); +#endif +#if CONFIG_INTC_CLIC_PLIC num += PLIC_IRQ_OFFSET; +#endif } else { num = irqn; } -#else -#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE - num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_SCLAIM, csi_get_cpu_id()); -#else - num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_MCLAIM, csi_get_cpu_id()); -#endif -#endif return num; -#endif /* end exx */ +#endif /* CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC */ + + return 0; } void soc_irq_end(uint32_t irq_num) diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/tick.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/tick.c index a5ac75b6b09..20193461f39 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/tick.c +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/tick.c @@ -72,10 +72,8 @@ void tick_irq_handler(void *arg) extern void xPortSysTickHandler(void); xPortSysTickHandler(); #elif defined(CONFIG_KERNEL_RTTHREAD) - rt_interrupt_enter(); extern void rt_tick_increase(void); rt_tick_increase(); - rt_interrupt_leave(); #else #endif #endif /* end CONFIG_AOS_OSAL */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv_common.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv_common.h index 1cabea2cac3..69d21ac5101 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv_common.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv_common.h @@ -68,7 +68,20 @@ #define __ASM_STR(x) #x #endif +#define __I volatile const /*!< Defines 'read only' permissions */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + #ifndef __ASSEMBLY__ + +#define RISCV_FENCE(p, s) \ + __asm__ __volatile__ ("fence " #p "," #s : : : "memory") + #define rv_csr_read(csr) \ ({ \ register unsigned long __v; \ @@ -121,69 +134,291 @@ : : "rK"(__v) \ : "memory"); \ }) + +#define rv_csr_read_write(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrrw %0, " __ASM_STR(csr) ", %1" \ + : "=r"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + + __ALWAYS_STATIC_INLINE uint8_t rv_readb(uintptr_t addr) + { + uint8_t val; + + val = *(volatile uint8_t *)addr; + RISCV_FENCE(ir, ir); + return val; + } + + __ALWAYS_STATIC_INLINE uint16_t rv_readw(uintptr_t addr) + { + uint16_t val; + + val = *(volatile uint16_t *)addr; + RISCV_FENCE(ir, ir); + return val; + } + + __ALWAYS_STATIC_INLINE uint32_t rv_readl(uintptr_t addr) + { + uint32_t val; + + val = *(volatile uint32_t *)addr; + RISCV_FENCE(ir, ir); + return val; + } + + __ALWAYS_STATIC_INLINE uint64_t rv_readq(uintptr_t addr) + { + uint64_t val; + + val = *(volatile uint64_t *)addr; + RISCV_FENCE(ir, ir); + return val; + } + + __ALWAYS_STATIC_INLINE void rv_writeb(uint8_t val, uintptr_t addr) + { + *(volatile uint8_t *)addr = val; + RISCV_FENCE(ow, ow); + } + + __ALWAYS_STATIC_INLINE void rv_writew(uint16_t val, uintptr_t addr) + { + *(volatile uint16_t *)addr = val; + RISCV_FENCE(ow, ow); + } + + __ALWAYS_STATIC_INLINE void rv_writel(uint32_t val, uintptr_t addr) + { + *(volatile uint32_t *)addr = val; + RISCV_FENCE(ow, ow); + } + + __ALWAYS_STATIC_INLINE void rv_writeq(uint64_t val, uintptr_t addr) + { + *(volatile uint64_t *)addr = val; + RISCV_FENCE(ow, ow); + } + +/** + \brief Get low 32 bits of MSTATEEN0 + \details Returns the current value of the MSTATEEN0 register. + \return MSTATEEN0 Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MSTATEEN0(void) +{ + volatile unsigned long result; + __ASM volatile("csrr %0, mstateen0" : "=r"(result)); + return (result); +} + +/** + \brief Set low 32 bits of of MSTATEEN0 + \details Assigns the given value to the MSTATEEN0 register. + \param [in] mstateen0 MSTATEEN0 value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSTATEEN0(unsigned long mstateen0) +{ + __ASM volatile("csrw mstateen0, %0" : : "r"(mstateen0)); +} + +/** + \brief Get high 32 bits of MSTATEEN0 + \details Returns the current value of the MSTATEEN0H register. + \return MSTATEEN0 Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MSTATEEN0H(void) +{ + volatile unsigned long result; + __ASM volatile("csrr %0, mstateen0h" : "=r"(result)); + return (result); +} + +/** + \brief Set high 32 bits of of MSTATEEN0 + \details Assigns the given value to the MSTATEEN0H register. + \param [in] mstateen0 MSTATEEN0 value to set + */ +__ALWAYS_STATIC_INLINE void __set_MSTATEEN0H(unsigned long mstateen0h) +{ + __ASM volatile("csrw mstateen0h, %0" : : "r"(mstateen0h)); +} + +/** + \brief Get MIREG + \details Returns the current value of the MIREG. + \return MIREG Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MIREG(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, mireg" : "=r"(result)); + return (result); +} + +/** + \brief Set MIREG + \details Assigns the given value to the MIREG. + \param [in] mireg MIREG value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIREG(unsigned long mireg) +{ + __ASM volatile("csrw mireg, %0" : : "r"(mireg)); +} + +/** + \brief Get MIREG2 + \details Returns the current value of the MIREG2. + \return MIREG2 Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MIREG2(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, mireg2" : "=r"(result)); + return (result); +} + +/** + \brief Set MIREG2 + \details Assigns the given value to the MIREG2. + \param [in] mireg2 MIREG2 value to set + */ +__ALWAYS_STATIC_INLINE void __set_MIREG2(unsigned long mireg2) +{ + __ASM volatile("csrw mireg2, %0" : : "r"(mireg2)); +} + +/** + \brief Get SIREG + \details Returns the current value of the SIREG. + \return SIREG Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SIREG(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, sireg" : "=r"(result)); + return (result); +} + +/** + \brief Set SIREG + \details Assigns the given value to the SIREG. + \param [in] sireg SIREG value to set + */ +__ALWAYS_STATIC_INLINE void __set_SIREG(unsigned long sireg) +{ + __ASM volatile("csrw sireg, %0" : : "r"(sireg)); +} + +/** + \brief Get SIREG2 + \details Returns the current value of the SIREG2. + \return SIREG2 Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SIREG2(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, sireg2" : "=r"(result)); + return (result); +} + +/** + \brief Set SIREG2 + \details Assigns the given value to the SIREG2. + \param [in] sireg2 SIREG2 value to set + */ +__ALWAYS_STATIC_INLINE void __set_SIREG2(unsigned long sireg2) +{ + __ASM volatile("csrw sireg2, %0" : : "r"(sireg2)); +} + +/** + \brief Get MISELECT + \details Returns the current value of the MISELECT. + \return MISELECT Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_MISELECT(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, miselect" : "=r"(result)); + return (result); +} + +/** + \brief Set MISELECT + \details Assigns the given value to the MISELECT. + \param [in] miselect MISELECT value to set + */ +__ALWAYS_STATIC_INLINE void __set_MISELECT(unsigned long miselect) +{ + __ASM volatile("csrw miselect, %0" : : "r"(miselect)); +} + +/** + \brief Get SISELECT + \details Returns the current value of the SISELECT. + \return SISELECT Register value + */ +__ALWAYS_STATIC_INLINE unsigned long __get_SISELECT(void) +{ + register unsigned long result; + __ASM volatile("csrr %0, siselect" : "=r"(result)); + return (result); +} + +/** + \brief Set SISELECT + \details Assigns the given value to the SISELECT. + \param [in] siselect SISELECT value to set + */ +__ALWAYS_STATIC_INLINE void __set_SISELECT(unsigned long siselect) +{ + __ASM volatile("csrw siselect, %0" : : "r"(siselect)); +} + +__ALWAYS_STATIC_INLINE uint8_t is_power_of_two(uint32_t x) +{ + return x && !(x & (x - 1)); +} + +__ALWAYS_STATIC_INLINE uint32_t log2_ulong(unsigned long x) +{ + uint32_t result = 0; + while (x > 1) { + x >>= 1; + result++; + } + return result; +} + +__ALWAYS_STATIC_INLINE unsigned long align_to_power_of_two(unsigned long size) +{ + if (size <= 1) { + return size; + } + +#if defined(__GNUC__) || defined(__clang__) + unsigned long leading_zeros = __builtin_clzl(size - 1); + return 1UL << ((sizeof(unsigned long) << 3) - leading_zeros); +#else + unsigned long value = size - 1; + value |= value >> 1; + value |= value >> 2; + value |= value >> 4; + value |= value >> 8; + value |= value >> 16; +#if __SIZEOF_LONG__ == 8 + value |= value >> 32; #endif + return value + 1; +#endif +} -#define CSR_MCOR 0x7c2 -#define CSR_MHCR 0x7c1 -#define CSR_MCCR2 0x7c3 -#define CSR_MHINT 0x7c5 -#define CSR_MHINT2 0x7cc -#define CSR_MHINT3 0x7cd -#define CSR_MHINT4 0x7ce -#define CSR_MXSTATUS 0x7c0 -#define CSR_PLIC_BASE 0xfc1 -#define CSR_MRMR 0x7c6 -#define CSR_MRVBR 0x7c7 -#define CSR_MCOUNTERWEN 0x7c9 -#define CSR_MSMPR 0x7f3 - -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_MCPUID 0xfc0 - -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MENVCFG 0x30a -#define CSR_MSTATUSH 0x310 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MTVAL 0x343 -#define CSR_MIP 0x344 -#define CSR_MTINST 0x34a -#define CSR_MTVAL2 0x34b - - /* Machine Memory Protection */ -#define CSR_PMPCFG0 0x3a0 -#define CSR_PMPCFG1 0x3a1 -#define CSR_PMPCFG2 0x3a2 -#define CSR_PMPCFG3 0x3a3 -#define CSR_PMPCFG4 0x3a4 -#define CSR_PMPCFG5 0x3a5 -#define CSR_PMPCFG6 0x3a6 -#define CSR_PMPCFG7 0x3a7 -#define CSR_PMPCFG8 0x3a8 -#define CSR_PMPCFG9 0x3a9 -#define CSR_PMPCFG10 0x3aa -#define CSR_PMPCFG11 0x3ab -#define CSR_PMPCFG12 0x3ac -#define CSR_PMPCFG13 0x3ad -#define CSR_PMPCFG14 0x3ae -#define CSR_PMPCFG15 0x3af -#define CSR_PMPADDR0 0x3b0 -#define CSR_PMPADDR1 0x3b1 -#define CSR_PMPADDR2 0x3b2 -#define CSR_PMPADDR3 0x3b3 -#define CSR_PMPADDR4 0x3b4 -#define CSR_PMPADDR5 0x3b5 -#define CSR_PMPADDR6 0x3b6 -#define CSR_PMPADDR7 0x3b7 +#endif /* __ASSEMBLY__ */ #endif /* __CSI_RV_COMMON_H__ */ - diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv_encoding.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv_encoding.h new file mode 100644 index 00000000000..cfd10b9683b --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv_encoding.h @@ -0,0 +1,807 @@ +/* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CSI_RV_ENCODING_H__ +#define __CSI_RV_ENCODING_H__ + +/* ===== User-level CSRs ===== */ + +/* User Trap Setup (N-extension) */ +#define CSR_USTATUS 0x000 +#define CSR_UIE 0x004 +#define CSR_UTVEC 0x005 + +/* User Trap Handling (N-extension) */ +#define CSR_USCRATCH 0x040 +#define CSR_UEPC 0x041 +#define CSR_UCAUSE 0x042 +#define CSR_UTVAL 0x043 +#define CSR_UIP 0x044 + +/* User Floating-point CSRs */ +#define CSR_FFLAGS 0x001 +#define CSR_FRM 0x002 +#define CSR_FCSR 0x003 + +/* User Vector CSRs */ +#define CSR_VSTART 0x008 +#define CSR_VXSAT 0x009 +#define CSR_VXRM 0x00A +#define CSR_VCSR 0x00F +#define CSR_VL 0xC20 +#define CSR_VTYPE 0xC21 +#define CSR_VLENB 0xC22 + +/* User Counters/Timers */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f + +/* ===== Supervisor-level CSRs ===== */ + +/* Supervisor Trap Setup */ +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 + +/* Supervisor Counter Overflow CSR */ +#define CSR_SCOUNTOVF 0xda0 + +/* Supervisor Configuration */ +#define CSR_SENVCFG 0x10a + +/* Supervisor Trap Handling */ +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 + +/* Supervisor CLIC CSRs */ +#define CSR_STVT 0x107 +#define CSR_SNXTI 0x145 +#define CSR_SINTSTATUS 0xDB1 +#define CSR_SINTTHRESH 0x147 +#define CSR_SSCRATCHCSW 0x148 +#define CSR_SSCRATCHCSWL 0x149 + +/* Sstc extension */ +#define CSR_STIMECMP 0x14D +#define CSR_STIMECMPH 0x15D + +/* Supervisor Protection and Translation */ +#define CSR_SATP 0x180 + +/* Supervisor Debug/Trace */ +#define CSR_SCONTEXT 0x5a8 + +/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ +#define CSR_SISELECT 0x150 +#define CSR_SIREG 0x151 +#define CSR_SIREG2 0x152 +#define CSR_SIREG3 0x153 +#define CSR_SIREG4 0x155 +#define CSR_SIREG5 0x156 +#define CSR_SIREG6 0x157 + +/* Supervisor-Level Interrupts (AIA) */ +#define CSR_STOPEI 0x15c +#define CSR_STOPI 0xdb0 + +/* Supervisor-Level High-Half CSRs (AIA) */ +#define CSR_SIEH 0x114 +#define CSR_SIPH 0x154 + +/* Supervisor stateen CSRs */ +#define CSR_SSTATEEN0 0x10C +#define CSR_SSTATEEN1 0x10D +#define CSR_SSTATEEN2 0x10E +#define CSR_SSTATEEN3 0x10F + +/* ===== Hypervisor-level CSRs ===== */ + +/* Hypervisor Trap Setup (H-extension) */ +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 + +/* Hypervisor Configuration */ +#define CSR_HENVCFG 0x60a +#define CSR_HENVCFGH 0x61a + +/* Hypervisor Trap Handling (H-extension) */ +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HTINST 0x64a +#define CSR_HGEIP 0xe12 + +/* Hypervisor Protection and Translation (H-extension) */ +#define CSR_HGATP 0x680 + +/* Hypervisor Counter/Timer Virtualization Registers (H-extension) */ +#define CSR_HTIMEDELTA 0x605 +#define CSR_HTIMEDELTAH 0x615 + +/* Virtual Supervisor Registers (H-extension) */ +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 + +/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ +#define CSR_HVIEN 0x608 +#define CSR_HVICTL 0x609 +#define CSR_HVIPRIO1 0x646 +#define CSR_HVIPRIO2 0x647 + +/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ +#define CSR_VSISELECT 0x250 +#define CSR_VSIREG 0x251 + +/* VS-Level Interrupts (H-extension with AIA) */ +#define CSR_VSTOPEI 0x25c +#define CSR_VSTOPI 0xeb0 + +/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ +#define CSR_HIDELEGH 0x613 +#define CSR_HVIENH 0x618 +#define CSR_HVIPH 0x655 +#define CSR_HVIPRIO1H 0x656 +#define CSR_HVIPRIO2H 0x657 +#define CSR_VSIEH 0x214 +#define CSR_VSIPH 0x254 + +/* Hypervisor stateen CSRs */ +#define CSR_HSTATEEN0 0x60C +#define CSR_HSTATEEN0H 0x61C +#define CSR_HSTATEEN1 0x60D +#define CSR_HSTATEEN1H 0x61D +#define CSR_HSTATEEN2 0x60E +#define CSR_HSTATEEN2H 0x61E +#define CSR_HSTATEEN3 0x60F +#define CSR_HSTATEEN3H 0x61F + +/* ===== Machine-level CSRs ===== */ + +/* Machine Information Registers */ +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 + +/* Machine Trap Setup */ +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSTATUSH 0x310 + +/* Machine Configuration */ +#define CSR_MENVCFG 0x30a +#define CSR_MENVCFGH 0x31a + +/* Machine Trap Handling */ +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_MTINST 0x34a +#define CSR_MTVAL2 0x34b + +/* Machine CLIC CSRs */ +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 +#define CSR_MINTSTATUS 0xFB1 +#define CSR_MINTTHRESH 0x347 +#define CSR_MSCRATCHCSW 0x348 +#define CSR_MSCRATCHCSWL 0x349 + +/* Machine Memory Protection */ +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPCFG4 0x3a4 +#define CSR_PMPCFG5 0x3a5 +#define CSR_PMPCFG6 0x3a6 +#define CSR_PMPCFG7 0x3a7 +#define CSR_PMPCFG8 0x3a8 +#define CSR_PMPCFG9 0x3a9 +#define CSR_PMPCFG10 0x3aa +#define CSR_PMPCFG11 0x3ab +#define CSR_PMPCFG12 0x3ac +#define CSR_PMPCFG13 0x3ad +#define CSR_PMPCFG14 0x3ae +#define CSR_PMPCFG15 0x3af +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_PMPADDR16 0x3c0 +#define CSR_PMPADDR17 0x3c1 +#define CSR_PMPADDR18 0x3c2 +#define CSR_PMPADDR19 0x3c3 +#define CSR_PMPADDR20 0x3c4 +#define CSR_PMPADDR21 0x3c5 +#define CSR_PMPADDR22 0x3c6 +#define CSR_PMPADDR23 0x3c7 +#define CSR_PMPADDR24 0x3c8 +#define CSR_PMPADDR25 0x3c9 +#define CSR_PMPADDR26 0x3ca +#define CSR_PMPADDR27 0x3cb +#define CSR_PMPADDR28 0x3cc +#define CSR_PMPADDR29 0x3cd +#define CSR_PMPADDR30 0x3ce +#define CSR_PMPADDR31 0x3cf +#define CSR_PMPADDR32 0x3d0 +#define CSR_PMPADDR33 0x3d1 +#define CSR_PMPADDR34 0x3d2 +#define CSR_PMPADDR35 0x3d3 +#define CSR_PMPADDR36 0x3d4 +#define CSR_PMPADDR37 0x3d5 +#define CSR_PMPADDR38 0x3d6 +#define CSR_PMPADDR39 0x3d7 +#define CSR_PMPADDR40 0x3d8 +#define CSR_PMPADDR41 0x3d9 +#define CSR_PMPADDR42 0x3da +#define CSR_PMPADDR43 0x3db +#define CSR_PMPADDR44 0x3dc +#define CSR_PMPADDR45 0x3dd +#define CSR_PMPADDR46 0x3de +#define CSR_PMPADDR47 0x3df +#define CSR_PMPADDR48 0x3e0 +#define CSR_PMPADDR49 0x3e1 +#define CSR_PMPADDR50 0x3e2 +#define CSR_PMPADDR51 0x3e3 +#define CSR_PMPADDR52 0x3e4 +#define CSR_PMPADDR53 0x3e5 +#define CSR_PMPADDR54 0x3e6 +#define CSR_PMPADDR55 0x3e7 +#define CSR_PMPADDR56 0x3e8 +#define CSR_PMPADDR57 0x3e9 +#define CSR_PMPADDR58 0x3ea +#define CSR_PMPADDR59 0x3eb +#define CSR_PMPADDR60 0x3ec +#define CSR_PMPADDR61 0x3ed +#define CSR_PMPADDR62 0x3ee +#define CSR_PMPADDR63 0x3ef + +/* Machine Counters/Timers */ +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +/* Machine Counter Setup */ +#define CSR_MCOUNTINHIBIT 0x320 +#define CSR_MCYCLECFG 0x321 +#define CSR_MINSTRETCFG 0x322 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f + +/* For RV32 */ +#define CSR_MCYCLECFGH 0x721 +#define CSR_MINSTRETCFGH 0x722 +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f + +/* Machine Security Configuration CSR (mseccfg) */ +#define CSR_MSECCFG 0x747 +#define CSR_MSECCFGH 0x757 + +/* Debug/Trace Registers */ +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_TINFO 0x7a4 +#define CSR_TCONTROL 0x7a5 +#define CSR_MCONTEXT 0x7a8 + +/* Debug Mode Registers */ +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH0 0x7b2 +#define CSR_DSCRATCH1 0x7b3 + +/* Machine-Level Window to Indirectly Accessed Registers */ +#define CSR_MISELECT 0x350 +#define CSR_MIREG 0x351 +#define CSR_MIREG2 0x352 +#define CSR_MIREG3 0x353 +#define CSR_MIREG4 0x355 +#define CSR_MIREG5 0x356 +#define CSR_MIREG6 0x357 + +/* Machine-Level Interrupts (AIA) */ +#define CSR_MTOPEI 0x35c +#define CSR_MTOPI 0xfb0 + +/* Virtual Interrupts for Supervisor Level (AIA) */ +#define CSR_MVIEN 0x308 +#define CSR_MVIP 0x309 + +/* Smstateen extension registers */ +/* Machine stateen CSRs */ +#define CSR_MSTATEEN0 0x30C +#define CSR_MSTATEEN0H 0x31C +#define CSR_MSTATEEN1 0x30D +#define CSR_MSTATEEN1H 0x31D +#define CSR_MSTATEEN2 0x30E +#define CSR_MSTATEEN2H 0x31E +#define CSR_MSTATEEN3 0x30F +#define CSR_MSTATEEN3H 0x31F + +/* Machine-Level High-Half CSRs (AIA) */ +#define CSR_MIDELEGH 0x313 +#define CSR_MIEH 0x314 +#define CSR_MVIENH 0x318 +#define CSR_MVIPH 0x319 +#define CSR_MIPH 0x354 + +/* XuanTie custom */ +/* Machine-Level XuanTie custom CSRs */ +#define CSR_MXSTATUS 0x7c0 +#define CSR_MHCR 0x7c1 +#define CSR_MCOR 0x7c2 +#define CSR_MCCR2 0x7c3 +#define CSR_MCER2 0x7c4 +#define CSR_MHINT 0x7c5 +#define CSR_MRMR 0x7c6 +#define CSR_MRVBR 0x7c7 +#define CSR_MCER 0x7c8 +#define CSR_MCOUNTERWEN 0x7c9 +#define CSR_MHINT2 0x7cc +#define CSR_MHINT3 0x7cd +#define CSR_MHINT4 0x7ce +#define CSR_MHPMEVENT0 0x7e0 +#define CSR_MHPMEVENT2 0x7e1 +#define CSR_MHPMCR 0x7f0 +#define CSR_MHPMSR 0x7f1 +#define CSR_MHPMER 0x7f2 +#define CSR_MSMPR 0x7f3 +#define CSR_MZONEID 0x7f5 +#define CSR_MLLCPID 0x7f6 +#define CSR_MLLWP 0x7f7 + +#define CSR_MCINS 0x7d2 +#define CSR_MCINDEX 0x7d3 +#define CSR_MCDATA0 0x7d4 +#define CSR_MCDATA1 0x7d5 +#define CSR_MEICR 0x7d6 +#define CSR_MEICR2 0x7d7 +#define CSR_MBEADDR 0x7d8 + +#define CSR_MCPUID 0xfc0 +#define CSR_MAPBADDR 0xfc1 + +#define CSR_MHALTCAUSE 0xfe0 +#define CSR_MDBGINFO 0xfe1 +#define CSR_MPCFIFO 0xfe2 +#define CSR_MDBGINFO2 0xfe3 + +#define CSR_MNASTATUS 0x8000000000000210 + +#define CSR_MRPLCNTLST 0xbd8 +#define CSR_MCACHELOCK 0xbd9 +#define CSR_MCACHERPLPRI0 0xbda +#define CSR_MCACHERPLPRI1 0xbdb +#define CSR_MCACHERPLPRI2 0xbdc +#define CSR_MCACHERPLPRI3 0xbdd +#define CSR_MCACHERPLPRI4 0xbde +#define CSR_MCACHERPLPRI5 0xbdf + +/* Supervisor-Level XuanTie custom CSRs */ +#define CSR_SXSTATUS 0x5c0 +#define CSR_SHCR 0x5c1 +#define CSR_SCER2 0x5c2 +#define CSR_SCER 0x5c3 +#define CSR_SHINT 0x5c6 +#define CSR_SHINT2 0x5c7 +#define CSR_SHPMINHIBIT 0x5c8 +#define CSR_SHPMCR 0x5c9 +#define CSR_SHPMSR 0x5ca +#define CSR_SHPMER 0x5cb +#define CSR_SL2PID 0x5cc +#define CSR_SL2WP 0x5cd +#define CSR_SBEADDR 0x5d0 +#define CSR_SSBEPA 0x5d1 +#define CSR_SSBEPA2 0x5d2 +#define CSR_SCYCLE 0x5e0 +#define CSR_SINSTRET 0x5e2 +#define CSR_SHPMCOUNTER3 0x5e3 +#define CSR_SHPMCOUNTER4 0x5e4 +#define CSR_SHPMCOUNTER5 0x5e5 +#define CSR_SHPMCOUNTER6 0x5e6 +#define CSR_SHPMCOUNTER7 0x5e7 +#define CSR_SHPMCOUNTER8 0x5e8 +#define CSR_SHPMCOUNTER9 0x5e9 +#define CSR_SHPMCOUNTER10 0x5ea +#define CSR_SHPMCOUNTER11 0x5eb +#define CSR_SHPMCOUNTER12 0x5ec +#define CSR_SHPMCOUNTER13 0x5ed +#define CSR_SHPMCOUNTER14 0x5ee +#define CSR_SHPMCOUNTER15 0x5ef +#define CSR_SHPMCOUNTER16 0x5f0 +#define CSR_SHPMCOUNTER17 0x5f1 +#define CSR_SHPMCOUNTER18 0x5f2 +#define CSR_SHPMCOUNTER19 0x5f3 +#define CSR_SHPMCOUNTER20 0x5f4 +#define CSR_SHPMCOUNTER21 0x5f5 +#define CSR_SHPMCOUNTER22 0x5f6 +#define CSR_SHPMCOUNTER23 0x5f7 +#define CSR_SHPMCOUNTER24 0x5f8 +#define CSR_SHPMCOUNTER25 0x5f9 +#define CSR_SHPMCOUNTER26 0x5fa +#define CSR_SHPMCOUNTER27 0x5fb +#define CSR_SHPMCOUNTER28 0x5fc +#define CSR_SHPMCOUNTER29 0x5fd +#define CSR_SHPMCOUNTER30 0x5fe +#define CSR_SHPMCOUNTER31 0x5ff +#define CSR_SCYCLEH 0x9e0 +#define CSR_SINSTRETH 0x9e2 +#define CSR_SHPMCOUNTER3H 0x9e3 +#define CSR_SHPMCOUNTER4H 0x9e4 +#define CSR_SHPMCOUNTER5H 0x9e5 +#define CSR_SHPMCOUNTER6H 0x9e6 +#define CSR_SHPMCOUNTER7H 0x9e7 +#define CSR_SHPMCOUNTER8H 0x9e8 +#define CSR_SHPMCOUNTER9H 0x9e9 +#define CSR_SHPMCOUNTER10H 0x9ea +#define CSR_SHPMCOUNTER11H 0x9eb +#define CSR_SHPMCOUNTER12H 0x9ec +#define CSR_SHPMCOUNTER13H 0x9ed +#define CSR_SHPMCOUNTER14H 0x9ee +#define CSR_SHPMCOUNTER15H 0x9ef +#define CSR_SHPMCOUNTER16H 0x9f0 +#define CSR_SHPMCOUNTER17H 0x9f1 +#define CSR_SHPMCOUNTER18H 0x9f2 +#define CSR_SHPMCOUNTER19H 0x9f3 +#define CSR_SHPMCOUNTER20H 0x9f4 +#define CSR_SHPMCOUNTER21H 0x9f5 +#define CSR_SHPMCOUNTER22H 0x9f6 +#define CSR_SHPMCOUNTER23H 0x9f7 +#define CSR_SHPMCOUNTER24H 0x9f8 +#define CSR_SHPMCOUNTER25H 0x9f9 +#define CSR_SHPMCOUNTER26H 0x9fa +#define CSR_SHPMCOUNTER27H 0x9fb +#define CSR_SHPMCOUNTER28H 0x9fc +#define CSR_SHPMCOUNTER29H 0x9fd +#define CSR_SHPMCOUNTER30H 0x9fe +#define CSR_SHPMCOUNTER31H 0x9ff + +#define CSR_SRPLCNTLST 0x9d8 +#define CSR_SCACHELOCK 0x9d9 +#define CSR_SCACHERPLPRI0 0x9da +#define CSR_SCACHERPLPRI1 0x9db +#define CSR_SCACHERPLPRI2 0x9dc +#define CSR_SCACHERPLPRI3 0x9dd +#define CSR_SCACHERPLPRI4 0x9de +#define CSR_SCACHERPLPRI5 0x9df + +/* User-Level XuanTie custom CSRs */ +#define CSR_TWCOUNTER 0x804 +#define CSR_FXCR 0x800 +#define CSR_XMRSTART 0x801 +#define CSR_XMCSR 0x802 +#define CSR_XMSIZE 0x803 +#define CSR_XMLENB 0xcc0 +#define CSR_XRLENB 0xcc1 +#define CSR_XMISA 0xcc2 + +#define CSR_URPLCNTLST 0x8e8 +#define CSR_UCACHELOCK 0x8e9 +#define CSR_UCACHERPLPRI0 0x8ea +#define CSR_UCACHERPLPRI1 0x8eb +#define CSR_UCACHERPLPRI2 0x8ec +#define CSR_UCACHERPLPRI3 0x8ed +#define CSR_UCACHERPLPRI4 0x8ee +#define CSR_UCACHERPLPRI5 0x8ef + +//////////////////////////////////////////////////////////////////////// +/* MMIO registers For xSelect */ +#ifndef CONFIG_SPMP_MMIO_BASE +#define SPMP_MMIO_BASE 0x80000E00UL +#else +#define SPMP_MMIO_BASE CONFIG_SPMP_MMIO_BASE +#endif +/* +miselect#0 mireg → spmpaddr[0], mireg2 → spmpcfg[0] +miselect#1 mireg → spmpaddr[1], mireg2 → spmpcfg[1] +… … +miselect#63 mireg → spmpaddr[63], mireg2 → spmpcfg[63] +*/ + +/* +siselect#0: sireg → spmpaddr[0], sireg2 → spmpcfg[0] +siselect#1: sireg → spmpaddr[1], sireg2 → spmpcfg[1] +… … +siselect#63: sireg → spmpaddr[63], sireg2 → spmpcfg[63] +*/ + +#define SPMP_MMIO_SPMPADDR0_SPMPCFG0 (SPMP_MMIO_BASE + 0x00) +#define SPMP_MMIO_SPMPADDR1_SPMPCFG1 (SPMP_MMIO_BASE + 0x01) +#define SPMP_MMIO_SPMPADDR2_SPMPCFG2 (SPMP_MMIO_BASE + 0x02) +#define SPMP_MMIO_SPMPADDR3_SPMPCFG3 (SPMP_MMIO_BASE + 0x03) +#define SPMP_MMIO_SPMPADDR4_SPMPCFG4 (SPMP_MMIO_BASE + 0x04) +#define SPMP_MMIO_SPMPADDR5_SPMPCFG5 (SPMP_MMIO_BASE + 0x05) +#define SPMP_MMIO_SPMPADDR6_SPMPCFG6 (SPMP_MMIO_BASE + 0x06) +#define SPMP_MMIO_SPMPADDR7_SPMPCFG7 (SPMP_MMIO_BASE + 0x07) +#define SPMP_MMIO_SPMPADDR8_SPMPCFG8 (SPMP_MMIO_BASE + 0x08) +#define SPMP_MMIO_SPMPADDR9_SPMPCFG9 (SPMP_MMIO_BASE + 0x09) +#define SPMP_MMIO_SPMPADDR10_SPMPCFG10 (SPMP_MMIO_BASE + 0x0A) +#define SPMP_MMIO_SPMPADDR11_SPMPCFG11 (SPMP_MMIO_BASE + 0x0B) +#define SPMP_MMIO_SPMPADDR12_SPMPCFG12 (SPMP_MMIO_BASE + 0x0C) +#define SPMP_MMIO_SPMPADDR13_SPMPCFG13 (SPMP_MMIO_BASE + 0x0D) +#define SPMP_MMIO_SPMPADDR14_SPMPCFG14 (SPMP_MMIO_BASE + 0x0E) +#define SPMP_MMIO_SPMPADDR15_SPMPCFG15 (SPMP_MMIO_BASE + 0x0F) +#define SPMP_MMIO_SPMPADDR16_SPMPCFG16 (SPMP_MMIO_BASE + 0x10) +#define SPMP_MMIO_SPMPADDR17_SPMPCFG17 (SPMP_MMIO_BASE + 0x11) +#define SPMP_MMIO_SPMPADDR18_SPMPCFG18 (SPMP_MMIO_BASE + 0x12) +#define SPMP_MMIO_SPMPADDR19_SPMPCFG19 (SPMP_MMIO_BASE + 0x13) +#define SPMP_MMIO_SPMPADDR20_SPMPCFG20 (SPMP_MMIO_BASE + 0x14) +#define SPMP_MMIO_SPMPADDR21_SPMPCFG21 (SPMP_MMIO_BASE + 0x15) +#define SPMP_MMIO_SPMPADDR22_SPMPCFG22 (SPMP_MMIO_BASE + 0x16) +#define SPMP_MMIO_SPMPADDR23_SPMPCFG23 (SPMP_MMIO_BASE + 0x17) +#define SPMP_MMIO_SPMPADDR24_SPMPCFG24 (SPMP_MMIO_BASE + 0x18) +#define SPMP_MMIO_SPMPADDR25_SPMPCFG25 (SPMP_MMIO_BASE + 0x19) +#define SPMP_MMIO_SPMPADDR26_SPMPCFG26 (SPMP_MMIO_BASE + 0x1A) +#define SPMP_MMIO_SPMPADDR27_SPMPCFG27 (SPMP_MMIO_BASE + 0x1B) +#define SPMP_MMIO_SPMPADDR28_SPMPCFG28 (SPMP_MMIO_BASE + 0x1C) +#define SPMP_MMIO_SPMPADDR29_SPMPCFG29 (SPMP_MMIO_BASE + 0x1D) +#define SPMP_MMIO_SPMPADDR30_SPMPCFG30 (SPMP_MMIO_BASE + 0x1E) +#define SPMP_MMIO_SPMPADDR31_SPMPCFG31 (SPMP_MMIO_BASE + 0x1F) +#define SPMP_MMIO_SPMPADDR32_SPMPCFG32 (SPMP_MMIO_BASE + 0x20) +#define SPMP_MMIO_SPMPADDR33_SPMPCFG33 (SPMP_MMIO_BASE + 0x21) +#define SPMP_MMIO_SPMPADDR34_SPMPCFG34 (SPMP_MMIO_BASE + 0x22) +#define SPMP_MMIO_SPMPADDR35_SPMPCFG35 (SPMP_MMIO_BASE + 0x23) +#define SPMP_MMIO_SPMPADDR36_SPMPCFG36 (SPMP_MMIO_BASE + 0x24) +#define SPMP_MMIO_SPMPADDR37_SPMPCFG37 (SPMP_MMIO_BASE + 0x25) +#define SPMP_MMIO_SPMPADDR38_SPMPCFG38 (SPMP_MMIO_BASE + 0x26) +#define SPMP_MMIO_SPMPADDR39_SPMPCFG39 (SPMP_MMIO_BASE + 0x27) +#define SPMP_MMIO_SPMPADDR40_SPMPCFG40 (SPMP_MMIO_BASE + 0x28) +#define SPMP_MMIO_SPMPADDR41_SPMPCFG41 (SPMP_MMIO_BASE + 0x29) +#define SPMP_MMIO_SPMPADDR42_SPMPCFG42 (SPMP_MMIO_BASE + 0x2A) +#define SPMP_MMIO_SPMPADDR43_SPMPCFG43 (SPMP_MMIO_BASE + 0x2B) +#define SPMP_MMIO_SPMPADDR44_SPMPCFG44 (SPMP_MMIO_BASE + 0x2C) +#define SPMP_MMIO_SPMPADDR45_SPMPCFG45 (SPMP_MMIO_BASE + 0x2D) +#define SPMP_MMIO_SPMPADDR46_SPMPCFG46 (SPMP_MMIO_BASE + 0x2E) +#define SPMP_MMIO_SPMPADDR47_SPMPCFG47 (SPMP_MMIO_BASE + 0x2F) +#define SPMP_MMIO_SPMPADDR48_SPMPCFG48 (SPMP_MMIO_BASE + 0x30) +#define SPMP_MMIO_SPMPADDR49_SPMPCFG49 (SPMP_MMIO_BASE + 0x31) +#define SPMP_MMIO_SPMPADDR50_SPMPCFG50 (SPMP_MMIO_BASE + 0x32) +#define SPMP_MMIO_SPMPADDR51_SPMPCFG51 (SPMP_MMIO_BASE + 0x33) +#define SPMP_MMIO_SPMPADDR52_SPMPCFG52 (SPMP_MMIO_BASE + 0x34) +#define SPMP_MMIO_SPMPADDR53_SPMPCFG53 (SPMP_MMIO_BASE + 0x35) +#define SPMP_MMIO_SPMPADDR54_SPMPCFG54 (SPMP_MMIO_BASE + 0x36) +#define SPMP_MMIO_SPMPADDR55_SPMPCFG55 (SPMP_MMIO_BASE + 0x37) +#define SPMP_MMIO_SPMPADDR56_SPMPCFG56 (SPMP_MMIO_BASE + 0x38) +#define SPMP_MMIO_SPMPADDR57_SPMPCFG57 (SPMP_MMIO_BASE + 0x39) +#define SPMP_MMIO_SPMPADDR58_SPMPCFG58 (SPMP_MMIO_BASE + 0x3A) +#define SPMP_MMIO_SPMPADDR59_SPMPCFG59 (SPMP_MMIO_BASE + 0x3B) +#define SPMP_MMIO_SPMPADDR60_SPMPCFG60 (SPMP_MMIO_BASE + 0x3C) +#define SPMP_MMIO_SPMPADDR61_SPMPCFG61 (SPMP_MMIO_BASE + 0x3D) +#define SPMP_MMIO_SPMPADDR62_SPMPCFG62 (SPMP_MMIO_BASE + 0x3E) +#define SPMP_MMIO_SPMPADDR63_SPMPCFG63 (SPMP_MMIO_BASE + 0x3F) +#define SPMP_MMIO_SSPMP_SWITCH_SWITCHH (SPMP_MMIO_BASE + 0x40) +#define SPMP_MMIO_MPMPDELEG (SPMP_MMIO_BASE + 0x41) + +#define PMP_MMIO_PMPSWITCH0 (0x800000c8) +#define PMP_MMIO_PMPSWITCH1 (0x800000c9) + +#endif /* __CSI_RV_ENCODING_H__ */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/csi_core.h b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/csi_core.h index 38efec98b36..64fe425cf21 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/csi_core.h +++ b/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/csi_core.h @@ -52,6 +52,7 @@ #elif defined(__riscv) +#include #if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \ || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP \ || CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT \ diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/SConscript b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/SConscript new file mode 100644 index 00000000000..a503a6e006c --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/SConscript @@ -0,0 +1,17 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = ['cpuport.c', 'interrupt.c'] +src += ['context_gcc.S', 'interrupt_gcc.S'] + +if GetDepend(['RT_USING_HW_ATOMIC']): + src += ['atomic_riscv.c'] + +if GetDepend(['RT_USING_SMP']): + src += ['cpuport_smp.c', 'clint.c'] + +group = DefineGroup('lib_cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/atomic_riscv.c b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/atomic_riscv.c new file mode 100644 index 00000000000..bc1561f2ee3 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/atomic_riscv.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-03-14 WangShun first version + */ + +#include + +rt_atomic_t rt_hw_atomic_exchange(volatile rt_atomic_t *ptr, rt_atomic_t val) +{ + rt_atomic_t result = 0; +#if __riscv_xlen == 32 + asm volatile ("amoswap.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#elif __riscv_xlen == 64 + asm volatile ("amoswap.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#endif + return result; +} + +rt_atomic_t rt_hw_atomic_add(volatile rt_atomic_t *ptr, rt_atomic_t val) +{ + rt_atomic_t result = 0; +#if __riscv_xlen == 32 + asm volatile ("amoadd.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#elif __riscv_xlen == 64 + asm volatile ("amoadd.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#endif + return result; +} + +rt_atomic_t rt_hw_atomic_sub(volatile rt_atomic_t *ptr, rt_atomic_t val) +{ + rt_atomic_t result = 0; + val = -val; +#if __riscv_xlen == 32 + asm volatile ("amoadd.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#elif __riscv_xlen == 64 + asm volatile ("amoadd.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#endif + return result; +} + +rt_atomic_t rt_hw_atomic_xor(volatile rt_atomic_t *ptr, rt_atomic_t val) +{ + rt_atomic_t result = 0; +#if __riscv_xlen == 32 + asm volatile ("amoxor.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#elif __riscv_xlen == 64 + asm volatile ("amoxor.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#endif + return result; +} + +rt_atomic_t rt_hw_atomic_and(volatile rt_atomic_t *ptr, rt_atomic_t val) +{ + rt_atomic_t result = 0; +#if __riscv_xlen == 32 + asm volatile ("amoand.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#elif __riscv_xlen == 64 + asm volatile ("amoand.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#endif + return result; +} + +rt_atomic_t rt_hw_atomic_or(volatile rt_atomic_t *ptr, rt_atomic_t val) +{ + rt_atomic_t result = 0; +#if __riscv_xlen == 32 + asm volatile ("amoor.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#elif __riscv_xlen == 64 + asm volatile ("amoor.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#endif + return result; +} + +rt_atomic_t rt_hw_atomic_load(volatile rt_atomic_t *ptr) +{ + rt_atomic_t result = 0; +#if __riscv_xlen == 32 + asm volatile ("amoxor.w %0, x0, (%1)" : "=r"(result) : "r"(ptr) : "memory"); +#elif __riscv_xlen == 64 + asm volatile ("amoxor.d %0, x0, (%1)" : "=r"(result) : "r"(ptr) : "memory"); +#endif + return result; +} + +void rt_hw_atomic_store(volatile rt_atomic_t *ptr, rt_atomic_t val) +{ + rt_atomic_t result = 0; +#if __riscv_xlen == 32 + asm volatile ("amoswap.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#elif __riscv_xlen == 64 + asm volatile ("amoswap.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); +#endif +} + +rt_atomic_t rt_hw_atomic_flag_test_and_set(volatile rt_atomic_t *ptr) +{ + rt_atomic_t result = 0; + rt_atomic_t temp = 1; +#if __riscv_xlen == 32 + asm volatile ("amoor.w %0, %1, (%2)" : "=r"(result) : "r"(temp), "r"(ptr) : "memory"); +#elif __riscv_xlen == 64 + asm volatile ("amoor.d %0, %1, (%2)" : "=r"(result) : "r"(temp), "r"(ptr) : "memory"); +#endif + return result; +} + +void rt_hw_atomic_flag_clear(volatile rt_atomic_t *ptr) +{ + rt_atomic_t result = 0; +#if __riscv_xlen == 32 + asm volatile ("amoand.w %0, x0, (%1)" : "=r"(result) :"r"(ptr) : "memory"); +#elif __riscv_xlen == 64 + asm volatile ("amoand.d %0, x0, (%1)" : "=r"(result) :"r"(ptr) : "memory"); +#endif +} + +rt_atomic_t rt_hw_atomic_compare_exchange_strong(volatile rt_atomic_t *ptr, rt_atomic_t *old, rt_atomic_t desired) +{ + rt_atomic_t tmp = *old; + rt_atomic_t result = 0; +#if __riscv_xlen == 32 + asm volatile( + " fence iorw, ow\n" + "1: lr.w.aq %[result], (%[ptr])\n" + " bne %[result], %[tmp], 2f\n" + " sc.w.rl %[tmp], %[desired], (%[ptr])\n" + " bnez %[tmp], 1b\n" + " li %[result], 1\n" + " j 3f\n" + " 2:sw %[result], (%[old])\n" + " li %[result], 0\n" + " 3:\n" + : [result]"+r" (result), [tmp]"+r" (tmp), [ptr]"+r" (ptr) + : [desired]"r" (desired), [old]"r"(old) + : "memory"); +#elif __riscv_xlen == 64 + asm volatile( + " fence iorw, ow\n" + "1: lr.d.aq %[result], (%[ptr])\n" + " bne %[result], %[tmp], 2f\n" + " sc.d.rl %[tmp], %[desired], (%[ptr])\n" + " bnez %[tmp], 1b\n" + " li %[result], 1\n" + " j 3f\n" + " 2:sd %[result], (%[old])\n" + " li %[result], 0\n" + " 3:\n" + : [result]"+r" (result), [tmp]"+r" (tmp), [ptr]"+r" (ptr) + : [desired]"r" (desired), [old]"r"(old) + : "memory"); +#endif + return result; +} diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/clint.c b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/clint.c new file mode 100644 index 00000000000..86e15f68226 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/clint.c @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/12/23 Bernard The first version + * 2018/12/27 Jesven Add secondary cpu boot + * 2023/11/10 WangShun Adapted to Xuantie C908MP + */ + +#include +#include +#include +#include +#include +#include +#include + +enum +{ + CRXX_MP_CORE0 = 0, + CRXX_MP_CORE1, + CRXX_MP_CORE2, + CRXX_MP_CORE3, + CRXX_MP_CORE4, + CRXX_MP_CORE5, + CRXX_MP_CORE6, + CRXX_MP_CORE7, +}; + +/** + * @brief This function is used to suspend a specified kernel software interrupt. + * + * @note Calling this function will trigger inter core interrupts. + * + * @param id is the ID of the specific physical core. + * + */ +void clint_ipi_send(uint64_t id) +{ + CLINT_Type *clint = (CLINT_Type *)CORET_BASE; + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + switch (id) + { + case CRXX_MP_CORE0: + clint->SSIP0 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE1: + clint->SSIP1 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE2: + clint->SSIP2 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE3: + clint->SSIP3 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE4: + clint->SSIP4 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE5: + clint->SSIP5 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE6: + clint->SSIP6 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE7: + clint->SSIP7 |= (uint32_t)0x1; + break; + default: + break; + } +#else + switch (id) + { + case CRXX_MP_CORE0: + clint->MSIP0 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE1: + clint->MSIP1 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE2: + clint->MSIP2 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE3: + clint->MSIP3 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE4: + clint->MSIP4 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE5: + clint->MSIP5 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE6: + clint->MSIP6 |= (uint32_t)0x1; + break; + case CRXX_MP_CORE7: + clint->MSIP7 |= (uint32_t)0x1; + break; + default: + break; + } +#endif +} + +/** + * @brief This function is used to clear the specified kernel software interrupt. + * + * @note Calling this function will clear the inter core interrupt suspend flag. + * + * @param id is the ID of the specific physical core. + * + */ +void clint_ipi_clear(uint64_t id) +{ + CLINT_Type *clint = (CLINT_Type *)CORET_BASE; + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + switch (id) + { + case CRXX_MP_CORE0: + clint->SSIP0 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE1: + clint->SSIP1 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE2: + clint->SSIP2 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE3: + clint->SSIP3 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE4: + clint->SSIP4 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE5: + clint->SSIP5 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE6: + clint->SSIP6 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE7: + clint->SSIP7 &= ~(uint32_t)0x1; + break; + default: + break; + } +#else + switch (id) + { + case CRXX_MP_CORE0: + clint->MSIP0 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE1: + clint->MSIP1 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE2: + clint->MSIP2 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE3: + clint->MSIP3 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE4: + clint->MSIP4 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE5: + clint->MSIP5 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE6: + clint->MSIP6 &= ~(uint32_t)0x1; + break; + case CRXX_MP_CORE7: + clint->MSIP7 &= ~(uint32_t)0x1; + break; + default: + break; + } +#endif +} + +/** + * @brief This function is used to configure timers for specific physical cores. + * + * @note Calling this function will configure Heartbeat Time. + * + * @param NULL. + * + */ +int rt_hw_tick_init(void) +{ + int core_id = rt_hw_cpu_id(); + + if (core_id == CRXX_MP_CORE0) + { + return 0; + } + csi_tick_init(); + return 0; +} + +/** + * @brief This function is used to enable software interrupts for specific physical cores. + * + * @note Calling this function will enable software interruption. + * + * @param NULL. + * + */ +int rt_hw_clint_ipi_enable(void) +{ + /* Set the Machine-Software bit in MIE */ + rv_csr_set(0x304, SR_MIE); + return 0; +} + +/** + * @brief This function is used to initialize the interrupt management function unique to the physical core. + * + * @note Calling this function will close the specific core external interrupt and set the trigger threshold to 0. + * + * @param NULL. + * + */ +void rt_hw_scondary_interrupt_init(void) +{ + int i; + int core_id = 0; + core_id = rt_hw_cpu_id(); + + if (core_id == CRXX_MP_CORE0) + { + return; + } + else if (core_id == CRXX_MP_CORE1) + { + for (i = 0; i < (CONFIG_IRQ_NUM + 31) / 32; i++) + { + PLIC->PLIC_H1_MIE[i] = 0; + PLIC->PLIC_H1_SIE[i] = 0; + } + + /* set hart threshold 0, enable all interrupt */ + PLIC->PLIC_H1_MTH = 0; + PLIC->PLIC_H1_STH = 0; + } + else if (core_id == CRXX_MP_CORE2) + { + for (i = 0; i < (CONFIG_IRQ_NUM + 31) / 32; i++) + { + PLIC->PLIC_H2_MIE[i] = 0; + PLIC->PLIC_H2_SIE[i] = 0; + } + + /* set hart threshold 0, enable all interrupt */ + PLIC->PLIC_H2_MTH = 0; + PLIC->PLIC_H2_STH = 0; + } + else if (core_id == CRXX_MP_CORE3) + { + for (i = 0; i < (CONFIG_IRQ_NUM + 31) / 32; i++) + { + PLIC->PLIC_H3_MIE[i] = 0; + PLIC->PLIC_H3_SIE[i] = 0; + } + + /* set hart threshold 0, enable all interrupt */ + PLIC->PLIC_H3_MTH = 0; + PLIC->PLIC_H3_STH = 0; + } + else if (core_id == CRXX_MP_CORE4) + { + for (i = 0; i < (CONFIG_IRQ_NUM + 31) / 32; i++) + { + PLIC->PLIC_H4_MIE[i] = 0; + PLIC->PLIC_H4_SIE[i] = 0; + } + + /* set hart threshold 0, enable all interrupt */ + PLIC->PLIC_H4_MTH = 0; + PLIC->PLIC_H4_STH = 0; + } + else if (core_id == CRXX_MP_CORE5) + { + for (i = 0; i < (CONFIG_IRQ_NUM + 31) / 32; i++) + { + PLIC->PLIC_H5_MIE[i] = 0; + PLIC->PLIC_H5_SIE[i] = 0; + } + + /* set hart threshold 0, enable all interrupt */ + PLIC->PLIC_H5_MTH = 0; + PLIC->PLIC_H5_STH = 0; + } + else if (core_id == CRXX_MP_CORE6) + { + for (i = 0; i < (CONFIG_IRQ_NUM + 31) / 32; i++) + { + PLIC->PLIC_H6_MIE[i] = 0; + PLIC->PLIC_H6_SIE[i] = 0; + } + + /* set hart threshold 0, enable all interrupt */ + PLIC->PLIC_H6_MTH = 0; + PLIC->PLIC_H6_STH = 0; + } + else if (core_id == CRXX_MP_CORE7) + { + for (i = 0; i < (CONFIG_IRQ_NUM + 31) / 32; i++) + { + PLIC->PLIC_H7_MIE[i] = 0; + PLIC->PLIC_H7_SIE[i] = 0; + } + + /* set hart threshold 0, enable all interrupt */ + PLIC->PLIC_H7_MTH = 0; + PLIC->PLIC_H7_STH = 0; + } + else + { + rt_kprintf("Illegal CPU core, ID = %d", core_id); + while (1) + ; + } + + /* enable MEIE & MSIE */ + uint32_t mie = __get_MIE(); + mie |= (1 << 11 | 1 << 7 | 1 << 3); +#if CONFIG_ECC_L1_ENABLE + mie |= (1 << 16); +#endif + __set_MIE(mie); +} + +/** + * @brief Software interrupt handling function. + * + * @note This function is used to respond to inter core interrupts. + * + * @param NULL. + * + */ +void ipi_irq(void) +{ + int core_id = 0; + core_id = rt_hw_cpu_id(); + clint_ipi_clear(core_id); + rt_schedule(); +} diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/context_gcc.S b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/context_gcc.S new file mode 100644 index 00000000000..d577c975783 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/context_gcc.S @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting implementation + * 2018/12/27 Jesven Add SMP support + * 2021/02/02 lizhirui Add userspace support + */ +#define __ASSEMBLY__ +#include "cpuport.h" +#include "stackframe.h" + + .global rt_hw_context_switch_to + .type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LOAD sp, (a0) + +#ifdef RT_USING_SMP + mv a0, a1 + call rt_cpus_lock_status_restore +#endif + RESTORE_ALL + mret + + .size rt_hw_context_switch_to, . - rt_hw_context_switch_to + +#ifdef RT_USING_SMP +/* + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * + * a0 --> from + * a1 --> to + * a2 --> to_thread + */ + .global rt_hw_context_switch + .type rt_hw_context_switch, %function +rt_hw_context_switch: + /* set mstatus.mpp */ + csrr t0, mxstatus + srli t0, t0, 30 + andi t0, t0, 0x3 + slli t0, t0, 11 + csrs mstatus, t0//if enter here,caller must be in system thread + csrw mepc, ra//return address + //saved from thread context + SAVE_ALL + + STORE sp, (a0) + + //restore to thread context + LOAD sp, (a1) + + mv a0, a2 + call rt_cpus_lock_status_restore + + RESTORE_ALL + mret + + .size rt_hw_context_switch, . - rt_hw_context_switch + +/* + * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * + * a0 --> context + * a1 --> from + * a2 --> to + * a3 --> to_thread + */ + .global rt_hw_context_switch_interrupt + .type rt_hw_context_switch_interrupt, %function +rt_hw_context_switch_interrupt: + + STORE a0, 0(a1) + + LOAD sp, 0(a2) + move a0, a3 + call rt_cpus_lock_status_restore + + RESTORE_ALL + mret + + .size rt_hw_context_switch_interrupt, . - rt_hw_context_switch_interrupt +#else +/* + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * + * a0 --> from + * a1 --> to + */ +/* + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread); + * + * a0 --> from + * a1 --> to + * a2 --> from_thread + * a3 --> to_thread + */ + .global rt_hw_context_switch + .type rt_hw_context_switch, %function + .global rt_hw_context_switch_interrupt + .type rt_hw_context_switch_interrupt, %function +rt_hw_context_switch: +rt_hw_context_switch_interrupt: + /* set rt_thread_switch_interrupt_flag to 1 */ + la t0, rt_thread_switch_interrupt_flag + LOAD t2, 0(t0) + bnez t2, _reswitch + li t1, 1 + STORE t1, 0(t0) + + /* set rt_interrupt_from_thread */ + la t0, rt_interrupt_from_thread + STORE a0, 0(t0) + +_reswitch: + /* set rt_interrupt_to_thread */ + la t0, rt_interrupt_to_thread + STORE a1, 0(t0) + +#if CONFIG_INTC_CLIC || CONFIG_INTC_CLIC_PLIC + /* trigger the tspend exception (causes context switch) */ + li t0, 0xE080100C + lb t1, (t0) + li t2, 0x01 + or t1, t1, t2 + sb t1, (t0) + + fence + nop + nop + nop + nop + nop + + ret +#else + /* trigger the tspend exception (causes context switch) */ + li t0, RISCV_VIC_TSPDR + li t2, 0x1 + sw t2, 0(t0) + +__loop: + lw t2, 0(t0) + seqz t1, t2 +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + csrr t2, sip + andi t2, t2, 0x2 +#else + csrr t2, mip + andi t2, t2, 0x8 +#endif + snez t3, t2 + add t2, t3, t1 + beqz t2, __loop + ret +#endif + + .size rt_hw_context_switch, . - rt_hw_context_switch + .size rt_hw_context_switch_interrupt, . - rt_hw_context_switch_interrupt +#endif /* RT_USING_SMP */ diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport.c b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport.c new file mode 100644 index 00000000000..117f400e7ab --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + * 2021-02-11 lizhirui add gp support + * 2021-11-19 JasonHu add fpu support + */ + +#include +#include +#include +#include +#include +#include "cpuport.h" +#include "stack.h" + +/** + * @brief from thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_from_thread = 0; +/** + * @brief to thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_to_thread = 0; +/** + * @brief flag to indicate context switch in interrupt or not + * + */ +volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; + + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct rt_hw_stack_frame *frame; + rt_uint8_t *stk; + int i; + extern int __global_pointer$; + + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); + + frame = (struct rt_hw_stack_frame *)stk; + + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) { + ((rt_ubase_t *)frame)[i] = i; + } + + frame->ra = (rt_ubase_t)texit; + frame->gp = (rt_ubase_t)&__global_pointer$; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + /* SPP=0b01 SPIE=0b10 */ + frame->mstatus = SR_SPP_S | SR_SPIE; /* sstatus */ +#else + /* MPP=0b11 MPIE=0b1 */ + frame->mstatus = SR_MPP_M | SR_MPIE; /* mstatus */ +#endif + frame->mstatus |= SR_SUM; + +#if defined(__riscv_dsp) && defined(ARCH_RISCV_DSP) + /* init vxsat */ + stk -= sizeof(rt_ubase_t); + *(rt_ubase_t *)stk = 0; +#endif + +#if defined(__riscv_flen) && defined(ARCH_RISCV_FPU) + int f_rgs_len; + f_rgs_len = sizeof(rt_hw_stack_f_frame_t); + stk -= f_rgs_len; + rt_hw_stack_f_frame_t *fframe = (rt_hw_stack_f_frame_t *)stk; + for (i = 0; i < f_rgs_len / sizeof(rt_ubase_t); i++) { + ((rt_ubase_t *)fframe)[i] = i; + } + + frame->mstatus |= SR_FS_INITIAL; /* enable FPU */ +#endif + +#if defined(__riscv_vector) && defined(ARCH_RISCV_VECTOR) + int vlenb = csi_vlenb_get_value(); + + stk -= sizeof(rt_hw_stack_v_frame_t); + rt_hw_stack_v_frame_t *vframe = (rt_hw_stack_v_frame_t *)stk; + vframe->vl = (rt_ubase_t)0; + vframe->vstart = (rt_ubase_t)0; + vframe->vtype = (rt_ubase_t)0; + vframe->vxsat = (rt_ubase_t)0; + vframe->vxrm = (rt_ubase_t)0; + + stk -= CTX_VECTOR_REG_NR * vlenb; + vframe = (rt_hw_stack_v_frame_t *)stk; + for (i = 0; i < CTX_VECTOR_REG_NR * vlenb / sizeof(rt_ubase_t); i++) { + ((rt_ubase_t *)vframe)[i] = i; + } + + frame->mstatus |= SR_VS_INITIAL; +#endif + +#if (defined(__riscv_matrix) || defined(__riscv_xtheadmatrix)) && defined(ARCH_RISCV_MATRIX) + int xmlenb = csi_xmlenb_get_value(); + + stk -= sizeof(rt_hw_stack_x_frame_t); + rt_hw_stack_x_frame_t *xframe = (rt_hw_stack_x_frame_t *)stk; + xframe->xmrstart = (rt_ubase_t)0; + xframe->xmcsr = (rt_ubase_t)0; + xframe->xmsize = (rt_ubase_t)0; + + stk -= xmlenb * 8; + xframe = (rt_hw_stack_x_frame_t *)stk; + for (i = 0; i < xmlenb * 8 / sizeof(rt_ubase_t); i++) { + ((rt_ubase_t *)xframe)[i] = i; + } + + frame->mstatus |= SR_MS_INITIAL; +#endif + + frame->x2 = (rt_ubase_t)stk; + return stk; +} +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * #else + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); + * #endif + */ +// #ifndef RT_USING_SMP +// void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread) +// { +// if (rt_thread_switch_interrupt_flag == 0) +// rt_interrupt_from_thread = from; + +// rt_interrupt_to_thread = to; +// rt_thread_switch_interrupt_flag = 1; + +// // rt_trigger_software_interrupt(); +// return ; +// } + +// #endif /* end of RT_USING_SMP */ + +int rt_hw_cpu_id(void) +{ + unsigned long long temp; + asm volatile("csrr %0, mhartid" : "=r" (temp) ); + return temp; +} + +void rt_hw_set_process_id(int pid) +{ + //TODO +} + +rt_bool_t rt_hw_interrupt_is_disabled(void) +{ + extern unsigned long cpu_is_irq_enable(); + return !cpu_is_irq_enable(); +} diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport.h b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport.h new file mode 100644 index 00000000000..d153c9b9d10 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + */ +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#ifdef RT_USING_SMP +typedef union { + unsigned long slock; + struct __arch_tickets { + unsigned short owner; + unsigned short next; + } tickets; +} rt_hw_spinlock_t; +#endif +#include + +/* bytes of register width */ +#if __riscv_xlen == 64 +#define STORE sd +#define LOAD ld +#define REGBYTES 8 +#else +#define STORE sw +#define LOAD lw +#define REGBYTES 4 +#endif + +#if defined(__riscv_flen) && defined(ARCH_RISCV_FPU) +#if __riscv_flen == 64 +#define FSTORE fsd +#define FLOAD fld +#define FREGBYTES 8 +#elif __riscv_flen == 32 +#define FSTORE fsw +#define FLOAD flw +#define FREGBYTES 4 +#endif +#endif + +#ifndef __riscv_32e +/* 33 general registers */ +#define CTX_GENERAL_REG_NR 33 +#else +/* 17 general registers */ +#define CTX_GENERAL_REG_NR 17 +#endif + +#if defined(__riscv_flen) && defined(ARCH_RISCV_FPU) +/* 32 fpu register */ +#define CTX_FPU_REG_NR 32 +/* 1 fpu csr register */ +#define CTX_FPU_CSR_REG_NR 1 +#else +#define CTX_FPU_REG_NR 0 +#define CTX_FPU_CSR_REG_NR 0 +#endif + +#if defined(__riscv_vector) && defined(ARCH_RISCV_VECTOR) +/* 32 vector registers */ +#define CTX_VECTOR_REG_NR 32 +/* 5 vector csr registers */ +#define CTX_VECTOR_CSR_REG_NR 5 +#else +#define CTX_VECTOR_REG_NR 0 +#define CTX_VECTOR_CSR_REG_NR 0 +#endif + +#if (defined(__riscv_matrix) || defined(__riscv_xtheadmatrix)) && defined(ARCH_RISCV_MATRIX) +/* 8 matrix registers */ +#define CTX_MATRIX_REG_NR 8 +/* 8 matrix csr registers */ +#define CTX_MATRIX_CSR_REG_NR 3 +#else +#define CTX_MATRIX_REG_NR 0 +#define CTX_MATRIX_CSR_REG_NR 0 +#endif + +#if defined(__riscv_dsp) && defined(ARCH_RISCV_DSP) +/* 1 dsp csr register */ +#define CTX_DSP_CSR_REG_NR 1 +#else +#define CTX_DSP_CSR_REG_NR 0 +#endif + +#ifdef CONFIG_VIC_TSPDR +#define VIC_TSPDR CONFIG_VIC_TSPDR +#else +#define VIC_TSPDR 0xE4000000 +#endif + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE +#define RISCV_VIC_TSPDR (VIC_TSPDR + 0xC000) /*soft irq register*/ +#else +#define RISCV_VIC_TSPDR (VIC_TSPDR) /*soft irq register*/ +#endif + +#ifndef __ASSEMBLY__ +#include + +int rt_hw_cpu_id(void); + +#endif + +#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport_smp.c b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport_smp.c new file mode 100644 index 00000000000..deedb3fd3ed --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/cpuport_smp.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/12/23 Bernard The first version + * 2018/12/27 Jesven Add secondary cpu boot + */ + +#include +#include +#include +#include +#include + +#ifdef RT_USING_SMP + +__attribute__((weak)) void riscv_soc_start_cpu(int cpu_num) +{ + //do nothing here. overide if necessary +} + +__attribute__((weak)) void riscv_soc_init_cpu(void) +{ + //do nothing here. overide if necessary +} + +typedef struct _spinlock +{ + long lock; +} spinlock_t; + +#define mb() \ + { \ + asm volatile("fence" :: \ + : "memory"); \ + } + +#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val) +#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr)) + +#ifndef __riscv_atomic +#error "atomic extension is required." +#endif +#define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc) +#define atomic_or(ptr, inc) __sync_fetch_and_or(ptr, inc) +#define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp) +#define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp) + +static inline int spinlock_trylock(spinlock_t *lock) +{ + int res = atomic_swap(&lock->lock, -1); + /* Use memory barrier to keep coherency */ + mb(); + return res; +} + +static inline void spinlock_lock(spinlock_t *lock) +{ + while(spinlock_trylock(lock)) + ; +} + +static inline void spinlock_unlock(spinlock_t *lock) +{ + /* Use memory barrier to keep coherency */ + mb(); + atomic_set(&lock->lock, 0); +} + +void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) +{ + ((spinlock_t *)lock)->lock = 0; +} + +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + spinlock_lock((spinlock_t *)lock); +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + spinlock_unlock((spinlock_t *)lock); +} + +extern void clint_ipi_send(uint64_t id); +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ + int idx; + for (idx = 0; idx < RT_CPUS_NR; idx ++) + { + if (cpu_mask & (1 << idx)) + { + clint_ipi_send(idx); + } + } +} + +extern rt_base_t secondary_boot_flag; +void rt_hw_secondary_cpu_up(void) +{ + for (int i = 1; i < RT_CPUS_NR; i++) { + riscv_soc_start_cpu(i); + } + mb(); + secondary_boot_flag = 0xa55a; +} + +extern void rt_hw_scondary_interrupt_init(void); +extern int rt_hw_tick_init(void); +extern int rt_hw_clint_ipi_enable(void); + +static void secondary_cpu_init(void) +{ + riscv_soc_init_cpu(); + + /* enable theadisaee & MM */ + unsigned long status = __get_MXSTATUS(); + status |= (1 << 22 | 1 << 15); +#if __riscv_matrix || __riscv_xtheadmatrix + /* enable matrix */ + status &= ~(1ul << 0); +#endif /* __riscv_matrix || __riscv_xtheadmatrix */ + __set_MXSTATUS(status); + +#if __riscv_flen + /* enable float ISA */ + status = __get_MSTATUS(); + status |= SR_FS_INITIAL; + __set_MSTATUS(status); +#endif +#ifdef __riscv_vector + /* enable vector ISA */ + status = __get_MSTATUS(); + status |= SR_VS_INITIAL; + __set_MSTATUS(status); +#endif +#if __riscv_matrix || __riscv_xtheadmatrix + /* enable matrix ISA */ + status = __get_MSTATUS(); + status |= SR_MS_INITIAL; + __set_MSTATUS(status); +#endif + +#if CONFIG_ECC_L1_ENABLE + /* enable L1 cache ecc */ + uint64_t mhint = __get_MHINT(); + mhint |= (0x1 << 19); + __set_MHINT(mhint); +#endif + +#if CONFIG_RISCV_SMODE + /* enable ecall delegate */ + unsigned long medeleg = __get_MEDELEG(); + medeleg |= (1 << 9); + __set_MEDELEG(medeleg); + + /* enable interrupt delegate */ + unsigned long mideleg = __get_MIDELEG(); + mideleg |= 0x222; + __set_MIDELEG(mideleg); +#endif + +#if CONFIG_RISCV_SMODE + /* enable mcounteren for s-mode */ + __set_MCOUNTEREN(0xffffffff); + +#if CBO_INSN_SUPPORT + unsigned long envcfg = __get_MENVCFG(); + /* enable CBIE & CBCFE & CBZE on lower priviledge */ + envcfg |= (3 << 4 | 1 << 6 | 1 << 7); + __set_MENVCFG(envcfg); +#endif +#endif +} + +void secondary_cpu_c_start(void) +{ + secondary_cpu_init(); + + rt_hw_spin_lock(&_cpus_lock); + + /* initialize interrupt controller */ + rt_hw_scondary_interrupt_init(); + + /* System timer initialization */ + rt_hw_tick_init(); + + rt_hw_clint_ipi_enable(); + + rt_system_scheduler_start(); +} + +void rt_hw_secondary_cpu_idle_exec(void) +{ + asm volatile ("wfi"); +} + +#endif /*RT_USING_SMP*/ diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/interrupt.c b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/interrupt.c new file mode 100644 index 00000000000..bba44db9e08 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/interrupt.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-19 JasonHu first version + */ + +#include +#include + +#include "rt_interrupt.h" + +extern rt_uint32_t rt_interrupt_nest; +extern rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +extern rt_uint32_t rt_thread_switch_interrupt_flag; + +struct rt_irq_desc isr_table[INTERRUPTS_MAX]; + +static void rt_hw_interrupt_handler(int vector, void *param) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_int32_t idx; + + rt_memset(isr_table, 0x00, sizeof(isr_table)); + for (idx = 0; idx < INTERRUPTS_MAX; idx++) + { + isr_table[idx].handler = rt_hw_interrupt_handler; + } + + /* init interrupt nest, and context in thread sp */ +#ifndef RT_USING_SMP + rt_interrupt_nest = 0; +#endif /* RT_USING_SMP */ + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + +} + +/** + + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param handler the interrupt service routine to be installed + * @param param the interrupt service function parameter + * @param name the interrupt name + * @return old handler + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + if ((vector < 0) || (vector > IRQ_MAX_NR)) + { + return old_handler; + } + + old_handler = isr_table[IRQ_OFFSET + vector].handler; + +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[IRQ_OFFSET + vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[IRQ_OFFSET + vector].handler = handler; + isr_table[IRQ_OFFSET + vector].param = param; + + return old_handler; +} diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/interrupt_gcc.S b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/interrupt_gcc.S new file mode 100644 index 00000000000..1f44d77ce5b --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/interrupt_gcc.S @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/02 Bernard The first version + * 2018/12/27 Jesven Add SMP schedule + * 2021/02/02 lizhirui Add userspace support + */ +#define __ASSEMBLY__ +#include "stackframe.h" + +.equ RISCV_MSTATUS_MIE, (1<<3) /*machine-level interrupt bit*/ + +.section .text.entry +.align 3 + +#ifdef RT_USING_SMP + .global Mcoret_Handler + .type Mcoret_Handler, %function +Mcoret_Handler: + SAVE_ALL + /* switch to interrupt stack */ + move s0, sp + + /* get cpu id */ + csrr t0, mhartid + + /* switch interrupt stack of current cpu */ + la sp, g_base_irqstack + addi t1, t0, 1 + li t2, CONFIG_ARCH_INTERRUPTSTACK + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ + + call CORET_IRQHandler + + # /* s0 --> sp */ + mv sp, s0 + mv a0, s0 + call rt_scheduler_do_irq_switch + + RESTORE_ALL + mret + + .size Mcoret_Handler, . - Mcoret_Handler +#endif + + .global Mtspend_Handler + .global tspend_handler + .type Mtspend_Handler, %function + .type tspend_handler, %function +Mtspend_Handler: +tspend_handler: + SAVE_ALL +#ifdef RT_USING_SMP + /* switch to interrupt stack */ + move s0, sp + + /* get cpu id */ + csrr t0, mhartid + + /* switch interrupt stack of current cpu */ + la sp, g_base_irqstack + addi t1, t0, 1 + li t2, CONFIG_ARCH_INTERRUPTSTACK + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ + call rt_interrupt_enter + call ipi_irq + call rt_interrupt_leave + + /* s0 --> sp */ + mv sp, s0 + mv a0, s0 + call rt_scheduler_do_irq_switch +#else + /* get rt_thread_switch_interrupt_flag */ + la t0, rt_thread_switch_interrupt_flag + LOAD t2, 0(t0) + beqz t2, tspend_exit /* tspend already handled */ + /* clear rt_thread_switch_interrupt_flag to 0 */ + STORE zero, 0(t0) + + /* switch thread */ + la t0, rt_interrupt_from_thread + LOAD t1, 0(t0) + STORE sp, 0(t1) + + la t0, rt_interrupt_to_thread + LOAD t1, 0(t0) + LOAD sp, 0(t1) + +tspend_exit: +#if CONFIG_INTC_CLIC || CONFIG_INTC_CLIC_PLIC +#else + /* clear tspend */ + li t0, RISCV_VIC_TSPDR + li t2, 0x0 + sw t2, 0(t0) +#endif +#endif /* RT_USING_SMP */ + + RESTORE_ALL + mret + + .size Mtspend_Handler, . - Mtspend_Handler + .size tspend_handler, . - tspend_handler + +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif + +.global cpu_intrpt_restore +.type cpu_intrpt_restore, %function +.global rt_hw_interrupt_enable +.type rt_hw_interrupt_enable, %function +cpu_intrpt_restore: +rt_hw_interrupt_enable: + csrs mstatus, a0 /* restore to old csr */ + jr ra + +.size cpu_intrpt_restore, . - cpu_intrpt_restore +.size rt_hw_interrupt_enable, . - rt_hw_interrupt_enable + +.global cpu_intrpt_save +.type cpu_intrpt_save, %function +.global rt_hw_interrupt_disable +.type rt_hw_interrupt_disable, %function +cpu_intrpt_save: +rt_hw_interrupt_disable: + csrrci a0, mstatus, 8 /* clear MIE */ + jr ra + +.size cpu_intrpt_save, . - cpu_intrpt_save +.size rt_hw_interrupt_disable, . - rt_hw_interrupt_disable + +.global cpu_is_irq_enable +.type cpu_is_irq_enable, %function +cpu_is_irq_enable: + csrr a0, mstatus + andi a0, a0, RISCV_MSTATUS_MIE + ret + +.size cpu_is_irq_enable, . - cpu_is_irq_enable diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/rt_interrupt.h b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/rt_interrupt.h new file mode 100644 index 00000000000..bdc98972b2c --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/rt_interrupt.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-19 JasonHu first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include + +#define NR_CPUS 1 + +#define IRQ_OFFSET 16 +#ifndef IRQ_MAX_NR +#define IRQ_MAX_NR 207 +#endif +#define INTERRUPTS_MAX (IRQ_OFFSET + IRQ_MAX_NR) + +enum { + EP_INSTRUCTION_ADDRESS_MISALIGNED = 0, + EP_INSTRUCTION_ACCESS_FAULT, + EP_ILLEGAL_INSTRUCTION, + EP_BREAKPOINT, + EP_LOAD_ADDRESS_MISALIGNED, + EP_LOAD_ACCESS_FAULT, + EP_STORE_ADDRESS_MISALIGNED, + EP_STORE_ACCESS_FAULT, + EP_ENVIRONMENT_CALL_U_MODE, + EP_ENVIRONMENT_CALL_S_MODE, + EP_RESERVED10, + EP_ENVIRONMENT_CALL_M_MODE, + EP_INSTRUCTION_PAGE_FAULT, /* page attr */ + EP_LOAD_PAGE_FAULT, /* read data */ + EP_RESERVED14, + EP_STORE_PAGE_FAULT, /* write data */ +}; + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); + +#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/stack.h b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/stack.h new file mode 100644 index 00000000000..89ab6e438b5 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/stack.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + * 2021-11-18 JasonHu add fpu member + */ + +#ifndef __STACK_H__ +#define __STACK_H__ + +#include +#include "cpuport.h" + +struct rt_hw_stack_frame +{ + rt_ubase_t ra; /* x1 - ra - return address for jumps 1*/ + rt_ubase_t x2; /* x2 - sp - stack pointer 2*/ + rt_ubase_t gp; /* x3 - gp - global pointer 3*/ + rt_ubase_t tp; /* x4 - tp - thread pointer 4*/ + rt_ubase_t t0; /* x5 - t0 - temporary register 0 5*/ + rt_ubase_t t1; /* x6 - t1 - temporary register 1 6*/ + rt_ubase_t t2; /* x7 - t2 - temporary register 2 7*/ + rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer 8*/ + rt_ubase_t s1; /* x9 - s1 - saved register 1 9*/ + rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 10*/ + rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 11*/ + rt_ubase_t a2; /* x12 - a2 - function argument 2 12*/ + rt_ubase_t a3; /* x13 - a3 - function argument 3 13*/ + rt_ubase_t a4; /* x14 - a4 - function argument 4 14*/ + rt_ubase_t a5; /* x15 - a5 - function argument 5 15*/ +#ifndef __riscv_32e + rt_ubase_t a6; /* x16 - a6 - function argument 6 16*/ + rt_ubase_t a7; /* x17 - s7 - function argument 7 17*/ + rt_ubase_t s2; /* x18 - s2 - saved register 2 18*/ + rt_ubase_t s3; /* x19 - s3 - saved register 3 19*/ + rt_ubase_t s4; /* x20 - s4 - saved register 4 20*/ + rt_ubase_t s5; /* x21 - s5 - saved register 5 21*/ + rt_ubase_t s6; /* x22 - s6 - saved register 6 22*/ + rt_ubase_t s7; /* x23 - s7 - saved register 7 23*/ + rt_ubase_t s8; /* x24 - s8 - saved register 8 24*/ + rt_ubase_t s9; /* x25 - s9 - saved register 9 25*/ + rt_ubase_t s10; /* x26 - s10 - saved register 10 26*/ + rt_ubase_t s11; /* x27 - s11 - saved register 11 27*/ + rt_ubase_t t3; /* x28 - t3 - temporary register 3 28*/ + rt_ubase_t t4; /* x29 - t4 - temporary register 4 29*/ + rt_ubase_t t5; /* x30 - t5 - temporary register 5 30*/ + rt_ubase_t t6; /* x31 - t6 - temporary register 6 31*/ +#endif + rt_ubase_t epc; /* epc - epc - program counter 32*/ + rt_ubase_t mstatus; /* - supervisor status register 33*/ +}; + +#if defined(__riscv_flen) && defined(ARCH_RISCV_FPU) +typedef struct { + rt_ubase_t fcsr; +#if __riscv_flen == 64 + uint64_t f[CTX_FPU_REG_NR]; /* f0~f31 */ +#elif __riscv_flen == 32 + uint32_t f[CTX_FPU_REG_NR]; /* f0~f31 */ +#endif +} __attribute__((__packed__)) rt_hw_stack_f_frame_t; +#endif /* __riscv_flen */ + +#if defined(__riscv_vector) && defined(ARCH_RISCV_VECTOR) +typedef struct { + rt_ubase_t vl; + rt_ubase_t vtype; + rt_ubase_t vstart; + rt_ubase_t vxsat; + rt_ubase_t vxrm; + rt_ubase_t v[]; /* v0~v31 */ +} rt_hw_stack_v_frame_t; +#endif + +#if (defined(__riscv_matrix) || defined(__riscv_xtheadmatrix)) && defined(ARCH_RISCV_MATRIX) +typedef struct { + rt_ubase_t xmrstart; + rt_ubase_t xmcsr; + rt_ubase_t xmsize; + rt_ubase_t x[]; /* M0 ~ M7 */ +} rt_hw_stack_x_frame_t; +#endif + +#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/stackframe.h b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/stackframe.h new file mode 100644 index 00000000000..32f5a4b2a8c --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/lib_cpu/stackframe.h @@ -0,0 +1,500 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-02 lizhirui first version + * 2021-02-11 lizhirui fixed gp save/store bug + * 2021-11-18 JasonHu add fpu registers save/restore + */ + +#ifndef __STACKFRAME_H__ +#define __STACKFRAME_H__ + +#include "cpuport.h" +#include "riscv_csr.h" + +#ifdef ARCH_RISCV_FPU +#define FPU_CTX_F0_OFF (__riscv_flen >> 5) * 0 /* offsetof(fpu_context_t, fpustatus.f[0]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F1_OFF (__riscv_flen >> 5) * 4 /* offsetof(fpu_context_t, fpustatus.f[1]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F2_OFF (__riscv_flen >> 5) * 8 /* offsetof(fpu_context_t, fpustatus.f[2]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F3_OFF (__riscv_flen >> 5) * 12 /* offsetof(fpu_context_t, fpustatus.f[3]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F4_OFF (__riscv_flen >> 5) * 16 /* offsetof(fpu_context_t, fpustatus.f[4]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F5_OFF (__riscv_flen >> 5) * 20 /* offsetof(fpu_context_t, fpustatus.f[5]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F6_OFF (__riscv_flen >> 5) * 24 /* offsetof(fpu_context_t, fpustatus.f[6]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F7_OFF (__riscv_flen >> 5) * 28 /* offsetof(fpu_context_t, fpustatus.f[7]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F8_OFF (__riscv_flen >> 5) * 32 /* offsetof(fpu_context_t, fpustatus.f[8]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F9_OFF (__riscv_flen >> 5) * 36 /* offsetof(fpu_context_t, fpustatus.f[9]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F10_OFF (__riscv_flen >> 5) * 40 /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F11_OFF (__riscv_flen >> 5) * 44 /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F12_OFF (__riscv_flen >> 5) * 48 /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F13_OFF (__riscv_flen >> 5) * 52 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F14_OFF (__riscv_flen >> 5) * 56 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F15_OFF (__riscv_flen >> 5) * 60 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F16_OFF (__riscv_flen >> 5) * 64 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F17_OFF (__riscv_flen >> 5) * 68 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F18_OFF (__riscv_flen >> 5) * 72 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F19_OFF (__riscv_flen >> 5) * 76 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F20_OFF (__riscv_flen >> 5) * 80 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F21_OFF (__riscv_flen >> 5) * 84 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F22_OFF (__riscv_flen >> 5) * 88 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F23_OFF (__riscv_flen >> 5) * 92 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F24_OFF (__riscv_flen >> 5) * 96 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F25_OFF (__riscv_flen >> 5) * 100 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F26_OFF (__riscv_flen >> 5) * 104 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F27_OFF (__riscv_flen >> 5) * 108 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F28_OFF (__riscv_flen >> 5) * 112 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F29_OFF (__riscv_flen >> 5) * 116 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F30_OFF (__riscv_flen >> 5) * 120 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#define FPU_CTX_F31_OFF (__riscv_flen >> 5) * 124 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */ +#endif /* ARCH_RISCV_FPU */ + +.macro SAVE_ALL + /* save general registers */ + STORE x2, (-CTX_GENERAL_REG_NR * REGBYTES + 1 * REGBYTES)(sp) // need store x2(sp) to stack first. + addi sp, sp, -CTX_GENERAL_REG_NR * REGBYTES + STORE x1, 0 * REGBYTES(sp) + STORE x3, 2 * REGBYTES(sp) + STORE x4, 3 * REGBYTES(sp) + STORE x5, 4 * REGBYTES(sp) + STORE x6, 5 * REGBYTES(sp) + STORE x7, 6 * REGBYTES(sp) + STORE x8, 7 * REGBYTES(sp) + STORE x9, 8 * REGBYTES(sp) + STORE x10, 9 * REGBYTES(sp) + STORE x11, 10 * REGBYTES(sp) + STORE x12, 11 * REGBYTES(sp) + STORE x13, 12 * REGBYTES(sp) + STORE x14, 13 * REGBYTES(sp) + STORE x15, 14 * REGBYTES(sp) +#ifndef __riscv_32e + STORE x16, 15 * REGBYTES(sp) + STORE x17, 16 * REGBYTES(sp) + STORE x18, 17 * REGBYTES(sp) + STORE x19, 18 * REGBYTES(sp) + STORE x20, 19 * REGBYTES(sp) + STORE x21, 20 * REGBYTES(sp) + STORE x22, 21 * REGBYTES(sp) + STORE x23, 22 * REGBYTES(sp) + STORE x24, 23 * REGBYTES(sp) + STORE x25, 24 * REGBYTES(sp) + STORE x26, 25 * REGBYTES(sp) + STORE x27, 26 * REGBYTES(sp) + STORE x28, 27 * REGBYTES(sp) + STORE x29, 28 * REGBYTES(sp) + STORE x30, 29 * REGBYTES(sp) + STORE x31, 30 * REGBYTES(sp) + csrr x1, mepc + STORE x1, 31 * REGBYTES(sp) + csrr t3, mstatus + STORE t3, 32 * REGBYTES(sp) +#else + csrr x1, mepc + STORE x1, 15 * REGBYTES(sp) + csrr x1, mstatus + STORE x1, 16 * REGBYTES(sp) +#endif + +#if defined(__riscv_dsp) && defined(ARCH_RISCV_DSP) + addi sp, sp, -CTX_DSP_CSR_REG_NR * REGBYTES + csrr t0, vxsat + STORE t0, 0(sp) +#endif + +#if defined(__riscv_flen) && defined(ARCH_RISCV_FPU) +#if CONFIG_CHECK_FPU_DIRTY + li t1, SR_FS_DIRTY + and t4, t3, t1 + bne t4, t1, 1f +#endif /* CONFIG_CHECK_FPU_DIRTY */ + /* save fcsr registers */ + addi sp, sp, -(CTX_FPU_CSR_REG_NR) * REGBYTES + frcsr t0 + STORE t0, (0)(sp) + /* save fpu registers*/ + addi sp, sp, -(CTX_FPU_REG_NR) * FREGBYTES + FSTORE f0, FPU_CTX_F0_OFF(sp) + FSTORE f1, FPU_CTX_F1_OFF(sp) + FSTORE f2, FPU_CTX_F2_OFF(sp) + FSTORE f3, FPU_CTX_F3_OFF(sp) + FSTORE f4, FPU_CTX_F4_OFF(sp) + FSTORE f5, FPU_CTX_F5_OFF(sp) + FSTORE f6, FPU_CTX_F6_OFF(sp) + FSTORE f7, FPU_CTX_F7_OFF(sp) + FSTORE f8, FPU_CTX_F8_OFF(sp) + FSTORE f9, FPU_CTX_F9_OFF(sp) + FSTORE f10, FPU_CTX_F10_OFF(sp) + FSTORE f11, FPU_CTX_F11_OFF(sp) + FSTORE f12, FPU_CTX_F12_OFF(sp) + FSTORE f13, FPU_CTX_F13_OFF(sp) + FSTORE f14, FPU_CTX_F14_OFF(sp) + FSTORE f15, FPU_CTX_F15_OFF(sp) + FSTORE f16, FPU_CTX_F16_OFF(sp) + FSTORE f17, FPU_CTX_F17_OFF(sp) + FSTORE f18, FPU_CTX_F18_OFF(sp) + FSTORE f19, FPU_CTX_F19_OFF(sp) + FSTORE f20, FPU_CTX_F20_OFF(sp) + FSTORE f21, FPU_CTX_F21_OFF(sp) + FSTORE f22, FPU_CTX_F22_OFF(sp) + FSTORE f23, FPU_CTX_F23_OFF(sp) + FSTORE f24, FPU_CTX_F24_OFF(sp) + FSTORE f25, FPU_CTX_F25_OFF(sp) + FSTORE f26, FPU_CTX_F26_OFF(sp) + FSTORE f27, FPU_CTX_F27_OFF(sp) + FSTORE f28, FPU_CTX_F28_OFF(sp) + FSTORE f29, FPU_CTX_F29_OFF(sp) + FSTORE f30, FPU_CTX_F30_OFF(sp) + FSTORE f31, FPU_CTX_F31_OFF(sp) +#if CONFIG_CHECK_FPU_DIRTY + j 2f +1: + /* don't store, move sp only */ + addi sp, sp, -(CTX_FPU_CSR_REG_NR * REGBYTES + CTX_FPU_REG_NR * FREGBYTES) +2: +#endif /* CONFIG_CHECK_FPU_DIRTY */ +#endif /* __riscv_flen && ARCH_RISCV_FPU */ + +#if defined(__riscv_vector) && defined(ARCH_RISCV_VECTOR) +#if CONFIG_CHECK_VECTOR_DIRTY + /* check if VS filed of MSTATUS is 'dirty' */ + li t1, SR_VS_DIRTY + and t4, t3, t1 + bne t4, t1, 3f +#endif + /* save vector csr registers */ + addi sp, sp, -(CTX_VECTOR_CSR_REG_NR) * REGBYTES + csrr t0, vl + STORE t0, (0)(sp) + csrr t0, vtype + STORE t0, (1 * REGBYTES)(sp) + csrr t0, vstart + STORE t0, (2 * REGBYTES)(sp) + csrr t0, vxsat + STORE t0, (3 * REGBYTES)(sp) + csrr t0, vxrm + STORE t0, (4 * REGBYTES)(sp) + /* save vector registers */ + csrr t0, vlenb + li t1, CTX_VECTOR_REG_NR + mul t2, t0, t1 + sub sp, sp, t2 + slli t0, t0, 3 + mv t1, sp +#if (__riscv_v == 7000) + vsetvli zero, zero, e8, m8 + vsb.v v0, (t1) + add t1, t1, t0 + vsb.v v8, (t1) + add t1, t1, t0 + vsb.v v16, (t1) + add t1, t1, t0 + vsb.v v24, (t1) +#elif (__riscv_v == 1000000) + vsetvli zero, zero, e8, m8, ta, ma + vs8r.v v0, (t1) + add t1, t1, t0 + vs8r.v v8, (t1) + add t1, t1, t0 + vs8r.v v16, (t1) + add t1, t1, t0 + vs8r.v v24, (t1) +#endif +#if CONFIG_CHECK_VECTOR_DIRTY + j 4f +3: + /* don't save, move sp only */ + addi sp, sp, -(CTX_VECTOR_CSR_REG_NR) * REGBYTES + csrr t0, vlenb + li t1, CTX_VECTOR_REG_NR + mul t2, t0, t1 + sub sp, sp, t2 +4: +#endif /* CONFIG_CHECK_VECTOR_DIRTY */ +#endif /* __riscv_vector && ARCH_RISCV_VECTOR */ +#if (defined(__riscv_matrix) || defined(__riscv_xtheadmatrix)) && defined(ARCH_RISCV_MATRIX) +#if CONFIG_CHECK_MATRIX_DIRTY + /* if not dirty, skip */ + li t1, SR_MS_DIRTY + and t4, t3, t1 + bne t4, t1, 5f +#endif + /* save matrix csr registers */ + addi sp, sp, -(CTX_MATRIX_CSR_REG_NR) * REGBYTES + csrr t0, xmrstart + STORE t0, (0)(sp) + csrr t0, xmcsr + STORE t0, (1 * REGBYTES)(sp) + csrr t0, xmsize + STORE t0, (2 * REGBYTES)(sp) + /* save matrix registers */ + csrr t0, xmlenb + slli t1, t0, 3 + sub sp, sp, t1 + csrw xmrstart, x0 + mst8mb m0, (sp) +#if CONFIG_CHECK_MATRIX_DIRTY + j 6f +5: + addi sp, sp, -(CTX_MATRIX_CSR_REG_NR) * REGBYTES + csrr t0, xmlenb + slli t1, t0, 3 + sub sp, sp, t1 +6: +#endif /* CONFIG_CHECK_MATRIX_DIRTY */ +#endif /* __riscv_matrix || __riscv_xtheadmatrix */ +.endm + +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY +.macro RESTORE_MSTATUS + li t1, 0 + +#if (defined(__riscv_matrix) || defined(__riscv_xtheadmatrix)) && defined(ARCH_RISCV_MATRIX) /* matrix registers */ + addi t1, t1, (CTX_MATRIX_CSR_REG_NR) * REGBYTES + csrr t0, xmlenb + slli t0, t0, 3 + add t1, t1, t0 +#endif /* __riscv_matrix || __riscv_xtheadmatrix */ +#if defined(__riscv_vector) && defined(ARCH_RISCV_VECTOR) + addi t1, t1, (CTX_VECTOR_CSR_REG_NR) * REGBYTES + csrr t0, vlenb + li t2, CTX_VECTOR_REG_NR + mul t2, t0, t2 + add t1, t1, t2 +#endif + +#if defined(__riscv_flen) && defined(ARCH_RISCV_FPU) + addi t1, t1, (CTX_FPU_CSR_REG_NR * REGBYTES + CTX_FPU_REG_NR * FREGBYTES) +#endif + + /* general regs */ + addi t1, t1, (CTX_GENERAL_REG_NR - 1) * REGBYTES + + /* restore mstatus */ + add sp, sp, t1 + LOAD t3, (0)(sp) + csrw mstatus, t3 + sub sp, sp, t1 +.endm +#endif /* CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY */ + +.macro RESTORE_ALL +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY + RESTORE_MSTATUS +#endif /* CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY */ + +#if (defined(__riscv_matrix) || defined(__riscv_xtheadmatrix)) && defined(ARCH_RISCV_MATRIX) +#if CONFIG_CHECK_MATRIX_DIRTY + /* if not dirty, skip */ + li t1, SR_MS_DIRTY + and t4, t3, t1 + bne t4, t1, 1f +#endif + /* restore matrix registers */ + csrr t0, xmlenb + slli t1, t0, 3 + csrw xmrstart, x0 + mst8mb m0, (sp) + add sp, sp, t1 + /* restore matrix csr registers */ + csrr t0, xmrstart + LOAD t0, (0)(sp) + csrr t0, xmcsr + LOAD t0, (1 * REGBYTES)(sp) + csrr t0, xmsize + LOAD t0, (2 * REGBYTES)(sp) + addi sp, sp, (CTX_MATRIX_CSR_REG_NR) * REGBYTES +#if CONFIG_CHECK_MATRIX_DIRTY + j 2f +1: + /* don't restore, move sp only */ + csrr t0, xmlenb + slli t1, t0, 3 + add sp, sp, t1 + addi sp, sp, (CTX_MATRIX_CSR_REG_NR) * REGBYTES +2: +#endif +#endif /* __riscv_matrix || __riscv_xtheadmatrix */ + +#if defined(__riscv_vector) && defined(ARCH_RISCV_VECTOR) +#if CONFIG_CHECK_VECTOR_DIRTY + /* restore mstatus first */ + /* check if VS filed of MSTATUS is 'dirty' */ + li t1, SR_VS_DIRTY + and t4, t3, t1 + bne t4, t1, 3f +#endif /* CONFIG_CHECK_VECTOR_DIRTY */ + /* restore vector registers */ + csrr t0, vlenb + slli t0, t0, 3 +#if (__riscv_v == 7000) + vsetvli zero, zero, e8, m8 + vlb.v v0, (sp) + add sp, sp, t0 + vlb.v v8, (sp) + add sp, sp, t0 + vlb.v v16, (sp) + add sp, sp, t0 + vlb.v v24, (sp) + add sp, sp, t0 +#elif (__riscv_v == 1000000) + vsetvli zero, zero, e8, m8, ta, ma + vl8r.v v0, (sp) + add sp, sp, t0 + vl8r.v v8, (sp) + add sp, sp, t0 + vl8r.v v16, (sp) + add sp, sp, t0 + vl8r.v v24, (sp) + add sp, sp, t0 +#endif + /* restore vector csr registers */ + LOAD t0, (0)(sp) + LOAD t1, (1 * REGBYTES)(sp) + LOAD t2, (2 * REGBYTES)(sp) + vsetvl zero, t0, t1 + csrw vstart, t2 + LOAD t2, (3 * REGBYTES)(sp) + csrw vxsat, t2 + LOAD t2, (4 * REGBYTES)(sp) + csrw vxrm, t2 + addi sp, sp, (CTX_VECTOR_CSR_REG_NR) * REGBYTES +#if CONFIG_CHECK_VECTOR_DIRTY + j 4f +3: + csrr t0, vlenb + li t1, CTX_VECTOR_REG_NR + mul t2, t0, t1 + add sp, sp, t2 + addi sp, sp, (CTX_VECTOR_CSR_REG_NR) * REGBYTES +4: +#endif /* CONFIG_CHECK_VECTOR_DIRTY */ +#endif /* __riscv_vector && ARCH_RISCV_VECTOR */ + +#if defined(__riscv_flen) && defined(ARCH_RISCV_FPU) +#if CONFIG_CHECK_FPU_DIRTY + /* check if FS filed of MSTATUS is 'dirty' */ + li t1, SR_FS_DIRTY + and t4, t3, t1 + bne t4, t1, 5f +#endif + /* restore float register */ + FLOAD f0, FPU_CTX_F0_OFF(sp) + FLOAD f1, FPU_CTX_F1_OFF(sp) + FLOAD f2, FPU_CTX_F2_OFF(sp) + FLOAD f3, FPU_CTX_F3_OFF(sp) + FLOAD f4, FPU_CTX_F4_OFF(sp) + FLOAD f5, FPU_CTX_F5_OFF(sp) + FLOAD f6, FPU_CTX_F6_OFF(sp) + FLOAD f7, FPU_CTX_F7_OFF(sp) + FLOAD f8, FPU_CTX_F8_OFF(sp) + FLOAD f9, FPU_CTX_F9_OFF(sp) + FLOAD f10,FPU_CTX_F10_OFF(sp) + FLOAD f11,FPU_CTX_F11_OFF(sp) + FLOAD f12,FPU_CTX_F12_OFF(sp) + FLOAD f13,FPU_CTX_F13_OFF(sp) + FLOAD f14,FPU_CTX_F14_OFF(sp) + FLOAD f15,FPU_CTX_F15_OFF(sp) + FLOAD f16,FPU_CTX_F16_OFF(sp) + FLOAD f17,FPU_CTX_F17_OFF(sp) + FLOAD f18,FPU_CTX_F18_OFF(sp) + FLOAD f19,FPU_CTX_F19_OFF(sp) + FLOAD f20,FPU_CTX_F20_OFF(sp) + FLOAD f21,FPU_CTX_F21_OFF(sp) + FLOAD f22,FPU_CTX_F22_OFF(sp) + FLOAD f23,FPU_CTX_F23_OFF(sp) + FLOAD f24,FPU_CTX_F24_OFF(sp) + FLOAD f25,FPU_CTX_F25_OFF(sp) + FLOAD f26,FPU_CTX_F26_OFF(sp) + FLOAD f27,FPU_CTX_F27_OFF(sp) + FLOAD f28,FPU_CTX_F28_OFF(sp) + FLOAD f29,FPU_CTX_F29_OFF(sp) + FLOAD f30,FPU_CTX_F30_OFF(sp) + FLOAD f31,FPU_CTX_F31_OFF(sp) + addi sp, sp, CTX_FPU_REG_NR * FREGBYTES + /* restore fcsr registers */ + LOAD t0, 0(sp) + fscsr t0 + addi sp, sp, CTX_FPU_CSR_REG_NR * REGBYTES +#if CONFIG_CHECK_FPU_DIRTY + j 6f +5: + addi sp, sp, CTX_FPU_REG_NR * FREGBYTES + addi sp, sp, CTX_FPU_CSR_REG_NR * REGBYTES +6: +#endif /* CONFIG_CHECK_FPU_DIRTY */ +#endif /* __riscv_flen && ARCH_RISCV_FPU */ + +#if defined(__riscv_dsp) && defined(ARCH_RISCV_DSP) + LOAD t0, 0(sp) + csrw vxsat, t0 + addi sp, sp, CTX_DSP_CSR_REG_NR * REGBYTES +#endif + + /* restore general registers */ +#ifndef __riscv_32e + LOAD x1, 31 * REGBYTES(sp) +#else + LOAD x1, 15 * REGBYTES(sp) +#endif + csrw mepc, x1 +#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) +#ifndef __riscv_32e + LOAD x1, 32 * REGBYTES(sp) +#else + LOAD x1, 16 * REGBYTES(sp) +#endif + csrw mstatus, x1 +#endif + LOAD x1, 0 * REGBYTES(sp) + LOAD x3, 2 * REGBYTES(sp) + LOAD x4, 3 * REGBYTES(sp) + LOAD x5, 4 * REGBYTES(sp) + LOAD x6, 5 * REGBYTES(sp) + LOAD x7, 6 * REGBYTES(sp) + LOAD x8, 7 * REGBYTES(sp) + LOAD x9, 8 * REGBYTES(sp) + LOAD x10, 9 * REGBYTES(sp) + LOAD x11, 10 * REGBYTES(sp) + LOAD x12, 11 * REGBYTES(sp) + LOAD x13, 12 * REGBYTES(sp) + LOAD x14, 13 * REGBYTES(sp) + LOAD x15, 14 * REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 15 * REGBYTES(sp) + LOAD x17, 16 * REGBYTES(sp) + LOAD x18, 17 * REGBYTES(sp) + LOAD x19, 18 * REGBYTES(sp) + LOAD x20, 19 * REGBYTES(sp) + LOAD x21, 20 * REGBYTES(sp) + LOAD x22, 21 * REGBYTES(sp) + LOAD x23, 22 * REGBYTES(sp) + LOAD x24, 23 * REGBYTES(sp) + LOAD x25, 24 * REGBYTES(sp) + LOAD x26, 25 * REGBYTES(sp) + LOAD x27, 26 * REGBYTES(sp) + LOAD x28, 27 * REGBYTES(sp) + LOAD x29, 28 * REGBYTES(sp) + LOAD x30, 29 * REGBYTES(sp) + LOAD x31, 30 * REGBYTES(sp) +#endif + addi sp, sp, CTX_GENERAL_REG_NR * REGBYTES +.endm + +.macro RESTORE_SYS_GP + .option push + .option norelax + la gp, __global_pointer$ + .option pop +.endm + +.macro OPEN_INTERRUPT + csrsi mstatus, 8 +.endm + +.macro CLOSE_INTERRUPT + csrci mstatus, 8 +.endm + +#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/pre_main/SConscript b/bsp/xuantie/libraries/xuantie_libraries/pre_main/SConscript index 4e2f4ed392d..79609527e73 100644 --- a/bsp/xuantie/libraries/xuantie_libraries/pre_main/SConscript +++ b/bsp/xuantie/libraries/xuantie_libraries/pre_main/SConscript @@ -4,7 +4,6 @@ import os cwd = GetCurrentDir() CPPPATH = [cwd] src = ['pre_main.c'] -src += ['libcpu.S'] group = DefineGroup('pre_main', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/xuantie/libraries/xuantie_libraries/pre_main/libcpu.S b/bsp/xuantie/libraries/xuantie_libraries/pre_main/libcpu.S deleted file mode 100644 index 184ba0c71f6..00000000000 --- a/bsp/xuantie/libraries/xuantie_libraries/pre_main/libcpu.S +++ /dev/null @@ -1,15 +0,0 @@ -#include "cpuport.h" - -.globl rt_hw_do_after_save_above -.type rt_hw_do_after_save_above,@function -rt_hw_do_after_save_above: -addi sp, sp, -4 - STORE ra, 0 * REGBYTES(sp) - - csrr a0, mscratch - call do_irq - - LOAD ra, 0 * REGBYTES(sp) - addi sp, sp, 4 - ret - \ No newline at end of file diff --git a/bsp/xuantie/smartl/e901/board/SConscript b/bsp/xuantie/smartl/e901/board/SConscript deleted file mode 100644 index a8088a7c1f5..00000000000 --- a/bsp/xuantie/smartl/e901/board/SConscript +++ /dev/null @@ -1,33 +0,0 @@ -import os -import rtconfig -from building import * - -Import('SDK_LIB') - -cwd = GetCurrentDir() - -# add general drivers -src = ['board.c'] - -path = [cwd] - -CPPDEFINES = [ - 'CONFIG_KERNEL_RTTHREAD=1', - '__RT_KERNEL_SOURCE__=1', - 'CONFIG_CSI_V2=1', - 'CONFIG_CSI=csi2', - 'CONFIG_INIT_TASK_STACK_SIZE=4096', - 'CONFIG_APP_TASK_STACK_SIZE=8192', - 'CONFIG_ARCH_MAINSTACK=4096', - 'CONFIG_ARCH_INTERRUPTSTACK=4096', - 'CONFIG_XIP=1', - 'CONFIG_LIBC_MINI_PRINTF_SUPPORT=1', - 'CONFIG_SYSTICK_HZ=100', - 'CONFIG_BOARD_SMARTL_EVB=1', - 'CONFIG_DEBUG=1', - 'CLI_CONFIG_STACK_SIZE=4096', - 'CONFIG_CPU_XUANTIE_E901PLUS_BM_CP=1', -] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) -Return('group') diff --git a/bsp/xuantie/smartl/e901/.config b/bsp/xuantie/smartl/e901plus/.config similarity index 97% rename from bsp/xuantie/smartl/e901/.config rename to bsp/xuantie/smartl/e901plus/.config index b9a9d9ca1da..c4b326caaca 100644 --- a/bsp/xuantie/smartl/e901/.config +++ b/bsp/xuantie/smartl/e901plus/.config @@ -1,4 +1,4 @@ -CONFIG_XUANTIAN_SMARTL_E901=y +CONFIG_XUANTIAN_SMARTL_E901PLUS=y # # RT-Thread Kernel @@ -181,7 +181,8 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -254,7 +255,7 @@ CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set @@ -282,8 +283,6 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_KTIME is not set -# CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -360,8 +359,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -370,6 +367,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -571,6 +569,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -595,7 +594,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -642,6 +643,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -736,6 +740,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -892,7 +897,24 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -938,9 +960,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -986,6 +1010,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_CST812T is not set # end of touch drivers +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -1065,6 +1090,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1413,6 +1443,5 @@ CONFIG_SOC_XUANTIE=y # CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y -# CONFIG_ENABLE_FPU is not set # end of On-chip Peripheral Drivers # end of Hardware Drivers Config diff --git a/bsp/xuantie/smartl/e901/.cproject b/bsp/xuantie/smartl/e901plus/.cproject similarity index 99% rename from bsp/xuantie/smartl/e901/.cproject rename to bsp/xuantie/smartl/e901plus/.cproject index d69a2d0740c..d384ed3ee22 100644 --- a/bsp/xuantie/smartl/e901/.cproject +++ b/bsp/xuantie/smartl/e901plus/.cproject @@ -74,7 +74,7 @@ - + @@ -89,7 +89,7 @@ - + @@ -145,7 +145,7 @@ - + @@ -314,7 +314,7 @@ - + @@ -369,7 +369,7 @@ - + @@ -538,7 +538,7 @@ - + @@ -593,7 +593,7 @@ - + @@ -762,7 +762,7 @@ - + @@ -816,7 +816,7 @@ - + diff --git a/bsp/xuantie/smartl/e901/.project b/bsp/xuantie/smartl/e901plus/.project similarity index 100% rename from bsp/xuantie/smartl/e901/.project rename to bsp/xuantie/smartl/e901plus/.project diff --git a/bsp/xuantie/smartl/e901/.settings/org.eclipse.core.runtime.prefs b/bsp/xuantie/smartl/e901plus/.settings/org.eclipse.core.runtime.prefs similarity index 100% rename from bsp/xuantie/smartl/e901/.settings/org.eclipse.core.runtime.prefs rename to bsp/xuantie/smartl/e901plus/.settings/org.eclipse.core.runtime.prefs diff --git a/bsp/xuantie/smartl/e901/.settings/projcfg.ini b/bsp/xuantie/smartl/e901plus/.settings/projcfg.ini similarity index 82% rename from bsp/xuantie/smartl/e901/.settings/projcfg.ini rename to bsp/xuantie/smartl/e901plus/.settings/projcfg.ini index b5f58371040..bb85923fe7f 100644 --- a/bsp/xuantie/smartl/e901/.settings/projcfg.ini +++ b/bsp/xuantie/smartl/e901plus/.settings/projcfg.ini @@ -17,4 +17,4 @@ project_type=rt-thread os_branch=master os_version=latest project_name=project -output_project_path=E:\rt-thread\bsp\xuantie\smartl\e901 \ No newline at end of file +output_project_path=E:\rt-thread\bsp\xuantie\smartl\e901plus \ No newline at end of file diff --git a/bsp/xuantie/smartl/e901/Kconfig b/bsp/xuantie/smartl/e901plus/Kconfig similarity index 90% rename from bsp/xuantie/smartl/e901/Kconfig rename to bsp/xuantie/smartl/e901plus/Kconfig index 9ed6a6ffd8c..2e77964d561 100644 --- a/bsp/xuantie/smartl/e901/Kconfig +++ b/bsp/xuantie/smartl/e901plus/Kconfig @@ -6,7 +6,7 @@ RTT_DIR := ../../../../ PKGS_DIR := packages -config XUANTIAN_SMARTL_E901 +config XUANTIAN_SMARTL_E901PLUS bool select ARCH_RISCV32 select RT_USING_COMPONENTS_INIT diff --git a/bsp/xuantie/smartl/e901/README.md b/bsp/xuantie/smartl/e901plus/README.md similarity index 98% rename from bsp/xuantie/smartl/e901/README.md rename to bsp/xuantie/smartl/e901plus/README.md index c597988039b..a25b44e3f6a 100644 --- a/bsp/xuantie/smartl/e901/README.md +++ b/bsp/xuantie/smartl/e901plus/README.md @@ -68,6 +68,11 @@ E901+ 处理器体系结构的主要特点如下： - BSP根目录下存在`qemu.bat`脚本，生成可执行文件后可点击该脚本直接启动QEMU. +- Linux用户可以直接使用`qemu-system-riscv32`命令启动QEMU. +```shell +qemu-system-riscv32 -machine smartl -nographic -kernel rtthread.elf -cpu e901plusbm-cp +``` + ## 二 工具 - 编译器： https://www.xrvm.cn/community/download?id=4433353576298909696 @@ -89,9 +94,6 @@ E901+ 处理器体系结构的主要特点如下： 生成可执行文件，可以直接在命令行启动qemu或者配置vscode脚本借助vscode强大的插件进行图形化调试，qemu的相关命令可以查看玄铁qemu的[用户手册](https://www.xrvm.cn/community/download?id=4397435198627713024)，下述是启动qemu的命令，在powershell或命令行可直接执行下述命令，注意qemu需要导出至环境变量或者使用绝对路径。 -```shell -qemu-system-riscv32 -machine smartl -nographic -kernel rtthread.elf -cpu e901plusbm-cp -``` 下述是使用vscode调试的展示。 diff --git a/bsp/xuantie/smartl/e901/SConscript b/bsp/xuantie/smartl/e901plus/SConscript similarity index 100% rename from bsp/xuantie/smartl/e901/SConscript rename to bsp/xuantie/smartl/e901plus/SConscript diff --git a/bsp/xuantie/smartl/e901/SConstruct b/bsp/xuantie/smartl/e901plus/SConstruct similarity index 96% rename from bsp/xuantie/smartl/e901/SConstruct rename to bsp/xuantie/smartl/e901plus/SConstruct index e26afa61dc9..d4dd24f330e 100644 --- a/bsp/xuantie/smartl/e901/SConstruct +++ b/bsp/xuantie/smartl/e901plus/SConstruct @@ -42,7 +42,7 @@ SDK_LIB = libraries_path_prefix Export('SDK_LIB') # prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True) bsp_vdir = 'build' library_vdir = 'build/libraries' diff --git a/bsp/xuantie/smartl/e901/applications/SConscript b/bsp/xuantie/smartl/e901plus/applications/SConscript similarity index 100% rename from bsp/xuantie/smartl/e901/applications/SConscript rename to bsp/xuantie/smartl/e901plus/applications/SConscript diff --git a/bsp/xuantie/smartl/e901/applications/main.c b/bsp/xuantie/smartl/e901plus/applications/main.c similarity index 100% rename from bsp/xuantie/smartl/e901/applications/main.c rename to bsp/xuantie/smartl/e901plus/applications/main.c diff --git a/bsp/xuantie/smartl/e901/board/Kconfig b/bsp/xuantie/smartl/e901plus/board/Kconfig similarity index 79% rename from bsp/xuantie/smartl/e901/board/Kconfig rename to bsp/xuantie/smartl/e901plus/board/Kconfig index 6abf0d16f47..de3ef342bd4 100644 --- a/bsp/xuantie/smartl/e901/board/Kconfig +++ b/bsp/xuantie/smartl/e901plus/board/Kconfig @@ -20,11 +20,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig ENABLE_FPU - bool "Enable FPU" - select ARCH_RISCV_FPU - default n - endmenu endmenu diff --git a/bsp/xuantie/smartl/e901plus/board/SConscript b/bsp/xuantie/smartl/e901plus/board/SConscript new file mode 100644 index 00000000000..41b3bfb657e --- /dev/null +++ b/bsp/xuantie/smartl/e901plus/board/SConscript @@ -0,0 +1,15 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = ['board.c'] + +path = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = ['']) +Return('group') diff --git a/bsp/xuantie/smartl/e901/board/board.c b/bsp/xuantie/smartl/e901plus/board/board.c similarity index 100% rename from bsp/xuantie/smartl/e901/board/board.c rename to bsp/xuantie/smartl/e901plus/board/board.c diff --git a/bsp/xuantie/xiaohui/c910/board/board.h b/bsp/xuantie/smartl/e901plus/board/board.h similarity index 97% rename from bsp/xuantie/xiaohui/c910/board/board.h rename to bsp/xuantie/smartl/e901plus/board/board.h index 77f1143abd8..9f95ecd3e58 100644 --- a/bsp/xuantie/xiaohui/c910/board/board.h +++ b/bsp/xuantie/smartl/e901plus/board/board.h @@ -17,7 +17,7 @@ */ /* - This is an example board.h for Board Compment, New Board should flow the macro defines. + This is an example board.h for Board Component, New Board should follow the macro defines. */ #ifndef __BOARD_H__ @@ -44,7 +44,7 @@ extern "C" { · WIFI · BT · AUDIO - BOARD_XXX Macro descripted below should be defined if the board support. + BOARD_XXX Macro described below should be defined if the board support. */ /****************************************************************************/ @@ -120,8 +120,8 @@ extern "C" { // UART /* - The total supported uart numbers on this board, 0 meas No uart support. - the BOARD_UART_XXX, x in rang of (0, BOARD_UART_NUM - 1) + The total supported uart numbers on this board, 0 means No uart support. + the BOARD_UART_XXX, x in range of (0, BOARD_UART_NUM - 1) */ #ifndef BOARD_UART_NUM #define BOARD_UART_NUM (1) diff --git a/bsp/xuantie/smartl/e901/figures/1.env.png b/bsp/xuantie/smartl/e901plus/figures/1.env.png similarity index 100% rename from bsp/xuantie/smartl/e901/figures/1.env.png rename to bsp/xuantie/smartl/e901plus/figures/1.env.png diff --git a/bsp/xuantie/smartl/e901/figures/2.scons.png b/bsp/xuantie/smartl/e901plus/figures/2.scons.png similarity index 100% rename from bsp/xuantie/smartl/e901/figures/2.scons.png rename to bsp/xuantie/smartl/e901plus/figures/2.scons.png diff --git a/bsp/xuantie/smartl/e901/figures/3.vscode.png b/bsp/xuantie/smartl/e901plus/figures/3.vscode.png similarity index 100% rename from bsp/xuantie/smartl/e901/figures/3.vscode.png rename to bsp/xuantie/smartl/e901plus/figures/3.vscode.png diff --git a/bsp/xuantie/smartl/e901/objdump.bat b/bsp/xuantie/smartl/e901plus/objdump.bat similarity index 79% rename from bsp/xuantie/smartl/e901/objdump.bat rename to bsp/xuantie/smartl/e901plus/objdump.bat index 020721c89a0..2b854815130 100644 --- a/bsp/xuantie/smartl/e901/objdump.bat +++ b/bsp/xuantie/smartl/e901plus/objdump.bat @@ -1,6 +1,6 @@ @echo off set OBJDUMP=D:\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\RISC-V\XTGccElfNewlib\V3.0.1\R\bin\riscv64-unknown-elf-objdump -set TARGET=E:\rt-thread\bsp\xuantie\smartl\e901\rtthread.elf +set TARGET=E:\rt-thread\bsp\xuantie\smartl\e901plus\rtthread.elf set OUTPUT=rtthread.asm %OBJDUMP% -d %TARGET% > %OUTPUT% diff --git a/bsp/xuantie/smartl/e901/qemu.bat b/bsp/xuantie/smartl/e901plus/qemu.bat similarity index 92% rename from bsp/xuantie/smartl/e901/qemu.bat rename to bsp/xuantie/smartl/e901plus/qemu.bat index 01e28b98172..7cef4db0811 100644 --- a/bsp/xuantie/smartl/e901/qemu.bat +++ b/bsp/xuantie/smartl/e901plus/qemu.bat @@ -31,9 +31,9 @@ if exist "!CONFIG_FILE!" ( :: Load CPU parameter from config file or set default if exist "!CPU_CONFIG_FILE!" ( set /p CPU_PARAM=<"!CPU_CONFIG_FILE!" - if not defined CPU_PARAM set "CPU_PARAM=e901" + if not defined CPU_PARAM set "CPU_PARAM=e901plusbm-cp" ) else ( - set "CPU_PARAM=e901" + set "CPU_PARAM=e901plusbm-cp" ) :: Prompt for new QEMU directory diff --git a/bsp/xuantie/smartl/e901/rtconfig.h b/bsp/xuantie/smartl/e901plus/rtconfig.h similarity index 97% rename from bsp/xuantie/smartl/e901/rtconfig.h rename to bsp/xuantie/smartl/e901plus/rtconfig.h index 6e2a5d3387d..d3d1c7f50f1 100644 --- a/bsp/xuantie/smartl/e901/rtconfig.h +++ b/bsp/xuantie/smartl/e901plus/rtconfig.h @@ -1,7 +1,7 @@ #ifndef RT_CONFIG_H__ #define RT_CONFIG_H__ -#define XUANTIAN_SMARTL_E901 +#define XUANTIAN_SMARTL_E901PLUS /* RT-Thread Kernel */ @@ -107,7 +107,8 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50201 +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -324,6 +325,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -416,4 +425,3 @@ /* end of Hardware Drivers Config */ #endif - diff --git a/bsp/xuantie/smartl/e901/rtconfig.py b/bsp/xuantie/smartl/e901plus/rtconfig.py similarity index 87% rename from bsp/xuantie/smartl/e901/rtconfig.py rename to bsp/xuantie/smartl/e901plus/rtconfig.py index a2253e216dc..4c1a2a509eb 100644 --- a/bsp/xuantie/smartl/e901/rtconfig.py +++ b/bsp/xuantie/smartl/e901plus/rtconfig.py @@ -1,6 +1,6 @@ import os ARCH = 'risc-v' -CPU = 'e901' +CPU = 'e901plus' # toolchains options CROSS_TOOL = 'gcc' @@ -27,6 +27,7 @@ if os.path.exists('./libraries'): LINK_FILE = './libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl_lite.ld' TARGET_NAME = 'rtthread.bin' +TARGET_ASM = 'rtthread.asm' #------- GCC settings ---------------------------------------------------------- if PLATFORM == 'gcc': @@ -55,14 +56,17 @@ '-DCONFIG_APP_TASK_STACK_SIZE=8192 ' '-DCONFIG_ARCH_MAINSTACK=4096 ' '-DCONFIG_ARCH_INTERRUPTSTACK=4096 ' + '-DCONFIG_INTC_CLIC=1 ' + '-DCONFIG_SUPPORT_IRQ_NESTED=0 ' '-DCONFIG_XIP=1 ' '-DCONFIG_LIBC_MINI_PRINTF_SUPPORT=1 ' - '-DCONFIG_SYSTICK_HZ=100 ' '-DCONFIG_BOARD_SMARTL_EVB=1 ' '-DCONFIG_DEBUG=1 ' '-DCLI_CONFIG_STACK_SIZE=4096 ' ) + GLOBAL_DEFINES += ' -DCONFIG_SYSTICK_HZ=RT_TICK_PER_SECOND ' + CFLAGS = DEVICE + ' -g -Wall -Wno-unused-function -Wformat -Wformat-security -Warray-bounds -Wuninitialized \ -Wreturn-type -Wcomment -Wswitch -Wparentheses -specs=minilibc.specs -MP -MMD -Os -Wpointer-arith \ -Wno-undef -ffunction-sections -fdata-sections -fno-inline-functions -fno-builtin \ @@ -71,9 +75,9 @@ AFLAGS = DEVICE + ' -g -Wall -Wno-unused-function -Wformat -Wformat-security -Warray-bounds -Wuninitialized \ -Wreturn-type -Wcomment -Wswitch -Wparentheses -specs=minilibc.specs -MP -MMD -Os -Wpointer-arith \ -Wno-undef -ffunction-sections -fdata-sections -fno-inline-functions -fno-builtin \ - -fno-strict-aliasing -Wno-char-subscripts -Wno-unused-but-set-variable ' + ' -MP -MMD -D"Default_IRQHandler=SW_handler" ' + GLOBAL_DEFINES + -fno-strict-aliasing -Wno-char-subscripts -Wno-unused-but-set-variable ' + GLOBAL_DEFINES - LFLAGS = DEVICE + ' -MP -MMD -Wl,-zmax-page-size=1024 -Wl,-Map=yoc.map -Wl,-zmax-page-size=1024 -Wl,-Map=yoc.map -Wl,--whole-archive -Wl,--no-whole-archive -specs=minilibc.specs -nostartfiles -Wl,--gc-sections ' + LFLAGS = DEVICE + ' -MP -MMD -Wl,-zmax-page-size=1024 -Wl,-Map=' + MAP_FILE + ' -Wl,--whole-archive -Wl,--no-whole-archive -specs=minilibc.specs -nostartfiles -Wl,--gc-sections ' LFLAGS += ' -T ' + LINK_FILE CPATH = '' @@ -88,6 +92,7 @@ CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' + POST_ACTION += OBJDUMP + ' -d $TARGET > ' + TARGET_ASM + '\n' POST_ACTION += SIZE + ' $TARGET\n' def dist_handle(BSP_ROOT, dist_dir): diff --git a/bsp/xuantie/smartl/e901/template.cdkproj b/bsp/xuantie/smartl/e901plus/template.cdkproj similarity index 100% rename from bsp/xuantie/smartl/e901/template.cdkproj rename to bsp/xuantie/smartl/e901plus/template.cdkproj diff --git a/bsp/xuantie/smartl/e901/template.cdkws b/bsp/xuantie/smartl/e901plus/template.cdkws similarity index 100% rename from bsp/xuantie/smartl/e901/template.cdkws rename to bsp/xuantie/smartl/e901plus/template.cdkws diff --git a/bsp/xuantie/smartl/e901/utilities/gdb.init b/bsp/xuantie/smartl/e901plus/utilities/gdb.init similarity index 100% rename from bsp/xuantie/smartl/e901/utilities/gdb.init rename to bsp/xuantie/smartl/e901plus/utilities/gdb.init diff --git a/bsp/xuantie/smartl/e902/.config b/bsp/xuantie/smartl/e902/.config index b7acc169028..c2c5a81af2c 100644 --- a/bsp/xuantie/smartl/e902/.config +++ b/bsp/xuantie/smartl/e902/.config @@ -105,8 +105,6 @@ CONFIG_XUANTIAN_SMARTL_E902=y # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options CONFIG_RT_NAME_MAX=12 @@ -183,7 +181,8 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -208,6 +207,7 @@ CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 # CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -255,7 +255,7 @@ CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set @@ -283,8 +283,6 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_KTIME is not set -# CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -361,8 +359,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -371,6 +367,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -572,6 +569,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -596,7 +594,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -643,6 +643,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -737,6 +740,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -893,7 +897,24 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -939,9 +960,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -987,6 +1010,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_CST812T is not set # end of touch drivers +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -1066,6 +1090,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1414,6 +1443,5 @@ CONFIG_SOC_XUANTIE=y # CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y -# CONFIG_ENABLE_FPU is not set # end of On-chip Peripheral Drivers # end of Hardware Drivers Config diff --git a/bsp/xuantie/smartl/e902/README.md b/bsp/xuantie/smartl/e902/README.md index 66841219a60..cdf2168eb23 100644 --- a/bsp/xuantie/smartl/e902/README.md +++ b/bsp/xuantie/smartl/e902/README.md @@ -41,7 +41,7 @@ E902 处理器体系结构的主要特点如下： - 当前BSP支持下述内核： ```asciiarmor - e902 e902m e902mt e902t + e902 e902m ``` - 当前BSP默认设置的内核是e902。 @@ -52,6 +52,11 @@ E902 处理器体系结构的主要特点如下： - BSP根目录下存在`qemu.bat`脚本，生成可执行文件后可点击该脚本直接启动QEMU. +- Linux用户可以直接使用`qemu-system-riscv32`命令启动QEMU. +```shell +qemu-system-riscv32 -machine smartl -nographic -kernel rtthread.elf -cpu e902 +``` + ## 二 工具 - 编译器： https://www.xrvm.cn/community/download?id=4433353576298909696 @@ -73,9 +78,6 @@ E902 处理器体系结构的主要特点如下： 生成可执行文件，可以直接在命令行启动qemu或者配置vscode脚本借助vscode强大的插件进行图形化调试，qemu的相关命令可以查看玄铁qemu的[用户手册](https://www.xrvm.cn/community/download?id=4397435198627713024)，下述是启动qemu的命令，在powershell或命令行可直接执行下述命令，注意qemu需要导出至环境变量或者使用绝对路径。 -```shell -qemu-system-riscv32 -machine smartl -nographic -kernel rtthread.elf -cpu e902 -``` 下述是使用vscode调试的展示。 diff --git a/bsp/xuantie/smartl/e902/SConstruct b/bsp/xuantie/smartl/e902/SConstruct index e26afa61dc9..d4dd24f330e 100644 --- a/bsp/xuantie/smartl/e902/SConstruct +++ b/bsp/xuantie/smartl/e902/SConstruct @@ -42,7 +42,7 @@ SDK_LIB = libraries_path_prefix Export('SDK_LIB') # prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True) bsp_vdir = 'build' library_vdir = 'build/libraries' diff --git a/bsp/xuantie/smartl/e902/board/Kconfig b/bsp/xuantie/smartl/e902/board/Kconfig index 6abf0d16f47..de3ef342bd4 100644 --- a/bsp/xuantie/smartl/e902/board/Kconfig +++ b/bsp/xuantie/smartl/e902/board/Kconfig @@ -20,11 +20,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig ENABLE_FPU - bool "Enable FPU" - select ARCH_RISCV_FPU - default n - endmenu endmenu diff --git a/bsp/xuantie/smartl/e902/board/SConscript b/bsp/xuantie/smartl/e902/board/SConscript index d36e734da17..41b3bfb657e 100644 --- a/bsp/xuantie/smartl/e902/board/SConscript +++ b/bsp/xuantie/smartl/e902/board/SConscript @@ -11,20 +11,5 @@ src = ['board.c'] path = [cwd] -CPPDEFINES = [ - 'CONFIG_KERNEL_RTTHREAD=1', - '__RT_KERNEL_SOURCE__=1', - 'CONFIG_CSI_V2=1', - 'CONFIG_CSI="csi2"', - 'CONFIG_SUPPORT_TSPEND=0', - 'CONFIG_SUPPORT_IRQ_NESTED=0', - 'CONFIG_XIP=1', - 'CONFIG_ARCH_MAINSTACK=4096', - 'CONFIG_ARCH_INTERRUPTSTACK=4096', - 'CONFIG_BOARD_SMARTL_EVB=1', - 'CLI_CONFIG_STACK_SIZE=4096', - 'CONFIG_CPU_XUANTIE_E902=1', -] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = ['']) Return('group') diff --git a/bsp/xuantie/smartl/e902/board/board.h b/bsp/xuantie/smartl/e902/board/board.h index 77f1143abd8..9f95ecd3e58 100644 --- a/bsp/xuantie/smartl/e902/board/board.h +++ b/bsp/xuantie/smartl/e902/board/board.h @@ -17,7 +17,7 @@ */ /* - This is an example board.h for Board Compment, New Board should flow the macro defines. + This is an example board.h for Board Component, New Board should follow the macro defines. */ #ifndef __BOARD_H__ @@ -44,7 +44,7 @@ extern "C" { · WIFI · BT · AUDIO - BOARD_XXX Macro descripted below should be defined if the board support. + BOARD_XXX Macro described below should be defined if the board support. */ /****************************************************************************/ @@ -120,8 +120,8 @@ extern "C" { // UART /* - The total supported uart numbers on this board, 0 meas No uart support. - the BOARD_UART_XXX, x in rang of (0, BOARD_UART_NUM - 1) + The total supported uart numbers on this board, 0 means No uart support. + the BOARD_UART_XXX, x in range of (0, BOARD_UART_NUM - 1) */ #ifndef BOARD_UART_NUM #define BOARD_UART_NUM (1) diff --git a/bsp/xuantie/smartl/e902/rtconfig.h b/bsp/xuantie/smartl/e902/rtconfig.h index 074033fb8f4..75da455020d 100644 --- a/bsp/xuantie/smartl/e902/rtconfig.h +++ b/bsp/xuantie/smartl/e902/rtconfig.h @@ -107,7 +107,8 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50201 +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define ARCH_RISCV @@ -324,6 +325,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/xuantie/smartl/e902/rtconfig.py b/bsp/xuantie/smartl/e902/rtconfig.py index 0d837041f1c..e3a1f56c5fc 100644 --- a/bsp/xuantie/smartl/e902/rtconfig.py +++ b/bsp/xuantie/smartl/e902/rtconfig.py @@ -27,6 +27,7 @@ if os.path.exists('./libraries'): LINK_FILE = './libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl.ld' TARGET_NAME = 'rtthread.bin' +TARGET_ASM = 'rtthread.asm' #------- GCC settings ---------------------------------------------------------- if PLATFORM == 'gcc': @@ -51,7 +52,7 @@ '-D__RT_KERNEL_SOURCE__=1 ' '-DCONFIG_CSI_V2=1 ' '-DCONFIG_CSI="csi2" ' - '-DCONFIG_SUPPORT_TSPEND=0 ' + '-DCONFIG_INTC_CLIC=1 ' '-DCONFIG_SUPPORT_IRQ_NESTED=0 ' '-DCONFIG_XIP=1 ' '-DCONFIG_ARCH_MAINSTACK=4096 ' @@ -60,14 +61,16 @@ '-DCLI_CONFIG_STACK_SIZE=4096 ' ) + GLOBAL_DEFINES += ' -DCONFIG_SYSTICK_HZ=RT_TICK_PER_SECOND ' + CFLAGS = DEVICE + ' -c -MP -MMD -Wno-unused-function -g -nostdlib -Wpointer-arith -Wno-undef -Wall -Wl,-EL \ -ffunction-sections -fdata-sections -fno-inline-functions -fno-builtin -fno-strict-aliasing \ -fno-strength-reduce -Os -g -Wall -Wunused -Wformat -Wformat-security -Warray-bounds -Wuninitialized \ -Wreturn-type -Wcomment -Wswitch -Wparentheses -Wlogical-op ' + GLOBAL_DEFINES - AFLAGS = DEVICE + ' -MP -MMD -D"Default_IRQHandler=SW_handler" ' + GLOBAL_DEFINES + AFLAGS = DEVICE + ' -MP -MMD ' + GLOBAL_DEFINES - LFLAGS = DEVICE + ' -MP -MMD -Wl,-zmax-page-size=1024 -Wl,-Map=yoc.map -Wl,-zmax-page-size=1024 -Wl,-Map=yoc.map -Wl,--whole-archive -Wl,--no-whole-archive -nostartfiles -Wl,--gc-sections ' + LFLAGS = DEVICE + ' -MP -MMD -Wl,-zmax-page-size=1024 -Wl,-Map=' + MAP_FILE + ' -Wl,--whole-archive -Wl,--no-whole-archive -nostartfiles -Wl,--gc-sections ' LFLAGS += ' -T ' + LINK_FILE CPATH = '' @@ -82,6 +85,7 @@ CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' + POST_ACTION += OBJDUMP + ' -d $TARGET > ' + TARGET_ASM + '\n' POST_ACTION += SIZE + ' $TARGET\n' def dist_handle(BSP_ROOT, dist_dir): diff --git a/bsp/xuantie/smartl/e906/.config b/bsp/xuantie/smartl/e906/.config index 701cf67f568..76998ca0221 100644 --- a/bsp/xuantie/smartl/e906/.config +++ b/bsp/xuantie/smartl/e906/.config @@ -1,5 +1,15 @@ CONFIG_XUANTIAN_SMARTL_E906=y +# +# CPU Architecture Features +# +CONFIG_ENABLE_FPU=y +# CONFIG_ARCH_RISCV_FPU_S is not set +CONFIG_ARCH_RISCV_FPU_D=y +CONFIG_ENABLE_DSP=y +CONFIG_ARCH_RISCV_DSP=y +# end of CPU Architecture Features + # # RT-Thread Kernel # @@ -105,8 +115,6 @@ CONFIG_XUANTIAN_SMARTL_E906=y # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options CONFIG_RT_NAME_MAX=12 @@ -127,10 +135,10 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set @@ -183,15 +191,14 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel CONFIG_ARCH_RISCV=y CONFIG_ARCH_RISCV_FPU=y -# CONFIG_ARCH_RISCV_FPU_S is not set -CONFIG_ARCH_RISCV_FPU_D=y CONFIG_ARCH_RISCV32=y # @@ -210,6 +217,8 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -242,7 +251,7 @@ CONFIG_RT_USING_SERIAL_V1=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_CLOCK_TIME is not set # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set @@ -270,8 +279,6 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_KTIME is not set -# CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -348,8 +355,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -358,6 +363,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -386,6 +392,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -493,6 +500,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QMODBUS is not set # CONFIG_PKG_USING_PNET is not set # CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set # end of IoT - internet of things # @@ -557,6 +565,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -581,7 +590,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -627,6 +638,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -720,6 +735,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RMP is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -802,6 +819,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_MM32 is not set @@ -844,6 +862,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # HC32 DDL Drivers # +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set # end of HC32 DDL Drivers # @@ -857,6 +879,38 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set # end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -902,9 +956,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -950,6 +1006,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_CST812T is not set # end of touch drivers +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -1028,6 +1085,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SEAN_WS2812B is not set # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1376,6 +1439,5 @@ CONFIG_SOC_XUANTIE=y # CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y -CONFIG_ENABLE_FPU=y # end of On-chip Peripheral Drivers # end of Hardware Drivers Config diff --git a/bsp/xuantie/smartl/e906/.cproject b/bsp/xuantie/smartl/e906/.cproject index 2026477b502..2b037fc8a35 100644 --- a/bsp/xuantie/smartl/e906/.cproject +++ b/bsp/xuantie/smartl/e906/.cproject @@ -47,7 +47,7 @@