diff --git a/fir4tap1016/README.md.txt b/fir4tap1016/README.md.txt new file mode 100644 index 0000000..073770e --- /dev/null +++ b/fir4tap1016/README.md.txt @@ -0,0 +1,16 @@ +# fir4tap1016 - 4-Tap Moving Average FIR Filter + +## Description +A fully synchronous, 4-tap moving average filter RTL IP block. This filter acts as a low-pass DSP module, designed to smooth out high-frequency noise in digital signal streams by continuously outputting the mean of the last four acquired samples utilizing an optimized shift-register pipeline. + +## Block Diagram +Refer to the comprehensive project report for detailed schematics and block diagrams. + +## Pin Configuration +* **Inputs (10):** clk (1), rst (1), data_in (8) +* **Outputs (16):** filter_out (16) + +## Author & Contact +* **Name:** Hanzala Zafar +* **Institution:** Jamia Millia Islamia +* **GitHub:** [@zafarhanzala](https://github.com/zafarhanzala) \ No newline at end of file diff --git a/fir4tap1016/Verilog_Files/moving_average_4tap.v b/fir4tap1016/Verilog_Files/moving_average_4tap.v new file mode 100644 index 0000000..9809897 --- /dev/null +++ b/fir4tap1016/Verilog_Files/moving_average_4tap.v @@ -0,0 +1,37 @@ +module moving_average_4tap ( + input wire clk, + input wire reset, + input wire [7:0] data_in, + output reg [7:0] data_out +); + + // The 4-stage pipeline registers to hold our samples + reg [7:0] reg1, reg2, reg3, reg4; + + // 10-bit wire for the sum to prevent overflow (8-bit + 8-bit + 8-bit + 8-bit = max 10 bits) + wire [9:0] sum; + + // Continuous combinational addition of the pipeline + assign sum = reg1 + reg2 + reg3 + reg4; + + // Sequential logic triggered on the clock edge + always @(posedge clk or posedge reset) begin + if (reset) begin + reg1 <= 8'd0; + reg2 <= 8'd0; + reg3 <= 8'd0; + reg4 <= 8'd0; + data_out <= 8'd0; + end else begin + // Shift the new data into the pipeline + reg1 <= data_in; + reg2 <= reg1; + reg3 <= reg2; + reg4 <= reg3; + + // Output the average (sum divided by 4) + data_out <= sum[9:2]; + end + end + +endmodule \ No newline at end of file diff --git a/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter-cache.lib b/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter-cache.lib new file mode 100644 index 0000000..98d3299 --- /dev/null +++ b/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter-cache.lib @@ -0,0 +1,153 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_8 +# +DEF dac_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# moving_average_4tap +# +DEF moving_average_4tap U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "moving_average_4tap" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 800 0 1 0 N +X clk0 1 2150 1900 200 R 50 50 1 1 I +X reset0 2 2150 1800 200 R 50 50 1 1 I +X data_in7 3 2150 1700 200 R 50 50 1 1 I +X data_in6 4 2150 1600 200 R 50 50 1 1 I +X data_in5 5 2150 1500 200 R 50 50 1 1 I +X data_in4 6 2150 1400 200 R 50 50 1 1 I +X data_in3 7 2150 1300 200 R 50 50 1 1 I +X data_in2 8 2150 1200 200 R 50 50 1 1 I +X data_in1 9 2150 1100 200 R 50 50 1 1 I +X data_in0 10 2150 1000 200 R 50 50 1 1 I +X data_out7 11 3550 1900 200 L 50 50 1 1 O +X data_out6 12 3550 1800 200 L 50 50 1 1 O +X data_out5 13 3550 1700 200 L 50 50 1 1 O +X data_out4 14 3550 1600 200 L 50 50 1 1 O +X data_out3 15 3550 1500 200 L 50 50 1 1 O +X data_out2 16 3550 1400 200 L 50 50 1 1 O +X data_out1 17 3550 1300 200 L 50 50 1 1 O +X data_out0 18 3550 1200 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.cir b/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.cir new file mode 100644 index 0000000..c192666 --- /dev/null +++ b/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.cir @@ -0,0 +1,26 @@ +* C:\FOSSEE\eSim-Workspace\4-Tap_MovingAverageFilter\4-Tap_MovingAverageFilter.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/26 14:21:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ moving_average_4tap +U2 Net-_U2-Pad1_ Net-_U1-Pad2_ adc_bridge_1 +U5 GND GND GND Net-_U5-Pad4_ GND GND GND GND Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ adc_bridge_8 +U6 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ /OUT_1 /OUT_2 /OUT_3 /OUT_4 /OUT_5 /OUT_6 /OUT_7 /OUT_8 dac_bridge_8 +v1 Net-_U2-Pad1_ GND pulse +v4 Net-_U5-Pad4_ GND pulse +U7 /OUT_1 plot_v1 +U8 /OUT_2 plot_v1 +U9 /OUT_8 plot_v1 +v2 Net-_U3-Pad1_ GND pulse +U3 Net-_U3-Pad1_ Net-_U1-Pad1_ adc_bridge_1 +U4 /OUT_3 plot_v1 +U10 /OUT_4 plot_v1 +U11 /OUT_5 plot_v1 +U12 /OUT_6 plot_v1 +U13 /OUT_7 plot_v1 + +.end diff --git a/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.pro b/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.pro new file mode 100644 index 0000000..e27a398 --- /dev/null +++ b/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.proj b/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.proj new file mode 100644 index 0000000..80e68ef --- /dev/null +++ b/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.proj @@ -0,0 +1 @@ +schematicFile 4-Tap_MovingAverageFilter.sch diff --git a/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.sch b/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.sch new file mode 100644 index 0000000..3e737de --- /dev/null +++ b/fir4tap1016/eSim_Project_Files/4-Tap_MovingAverageFilter.sch @@ -0,0 +1,394 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L moving_average_4tap U1 +U 1 1 69B5121A +P 2700 4400 +F 0 "U1" H 5550 6200 60 0000 C CNN +F 1 "moving_average_4tap" H 5550 6400 60 0000 C CNN +F 2 "" H 5550 6350 60 0000 C CNN +F 3 "" H 5550 6350 60 0000 C CNN + 1 2700 4400 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U2 +U 1 1 69B51353 +P 4150 2050 +F 0 "U2" H 4150 2050 60 0000 C CNN +F 1 "adc_bridge_1" H 4150 2200 60 0000 C CNN +F 2 "" H 4150 2050 60 0000 C CNN +F 3 "" H 4150 2050 60 0000 C CNN + 1 4150 2050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U5 +U 1 1 69B5137E +P 4300 2750 +F 0 "U5" H 4300 2750 60 0000 C CNN +F 1 "adc_bridge_8" H 4300 2900 60 0000 C CNN +F 2 "" H 4300 2750 60 0000 C CNN +F 3 "" H 4300 2750 60 0000 C CNN + 1 4300 2750 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_8 U6 +U 1 1 69B513B5 +P 6850 2550 +F 0 "U6" H 6850 2550 60 0000 C CNN +F 1 "dac_bridge_8" H 6850 2700 60 0000 C CNN +F 2 "" H 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2850 50 0001 C CNN +F 1 "GND" H 3700 2950 50 0000 C CNN +F 2 "" H 3700 3100 50 0001 C CNN +F 3 "" H 3700 3100 50 0001 C CNN + 1 3700 3100 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR07 +U 1 1 69B517FE +P 3700 3200 +F 0 "#PWR07" H 3700 2950 50 0001 C CNN +F 1 "GND" H 3700 3050 50 0000 C CNN +F 2 "" H 3700 3200 50 0001 C CNN +F 3 "" H 3700 3200 50 0001 C CNN + 1 3700 3200 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR08 +U 1 1 69B51826 +P 3700 3300 +F 0 "#PWR08" H 3700 3050 50 0001 C CNN +F 1 "GND" H 3700 3150 50 0000 C CNN +F 2 "" H 3700 3300 50 0001 C CNN +F 3 "" H 3700 3300 50 0001 C CNN + 1 3700 3300 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR09 +U 1 1 69B5184E +P 3700 3400 +F 0 "#PWR09" H 3700 3150 50 0001 C CNN +F 1 "GND" H 3700 3250 50 0000 C CNN +F 2 "" H 3700 3400 50 0001 C CNN +F 3 "" H 3700 3400 50 0001 C CNN + 1 3700 3400 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 69B51CE2 +P 7500 2700 +F 0 "U7" H 7500 3200 60 0000 C CNN +F 1 "plot_v1" H 7700 3050 60 0000 C CNN +F 2 "" H 7500 2700 60 0000 C CNN +F 3 "" H 7500 2700 60 0000 C CNN + 1 7500 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7400 2500 7500 2500 +Wire Wire Line + 7400 2600 8050 2600 +$Comp +L plot_v1 U8 +U 1 1 69B51E02 +P 8050 2800 +F 0 "U8" H 8050 3300 60 0000 C CNN +F 1 "plot_v1" H 8250 3150 60 0000 C CNN +F 2 "" H 8050 2800 60 0000 C CNN +F 3 "" H 8050 2800 60 0000 C CNN + 1 8050 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7400 3200 8450 3200 +Wire Wire Line + 8450 3200 8450 3250 +$Comp +L plot_v1 U9 +U 1 1 69B5215F +P 8450 3050 +F 0 "U9" H 8450 3550 60 0000 C CNN +F 1 "plot_v1" H 8650 3400 60 0000 C CNN +F 2 "" H 8450 3050 60 0000 C CNN +F 3 "" H 8450 3050 60 0000 C CNN + 1 8450 3050 + -1 0 0 1 +$EndComp +$Comp +L pulse v2 +U 1 1 69B52518 +P 3150 1300 +F 0 "v2" H 2950 1400 60 0000 C CNN +F 1 "pulse" H 2950 1250 60 0000 C CNN +F 2 "R1" H 2850 1300 60 0000 C CNN +F 3 "" H 3150 1300 60 0000 C CNN + 1 3150 1300 + 0 1 1 0 +$EndComp +$Comp +L adc_bridge_1 U3 +U 1 1 69B5258F +P 4250 1700 +F 0 "U3" H 4250 1700 60 0000 C CNN +F 1 "adc_bridge_1" H 4250 1850 60 0000 C CNN +F 2 "" H 4250 1700 60 0000 C CNN +F 3 "" H 4250 1700 60 0000 C CNN + 1 4250 1700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 1300 3600 1650 +Wire Wire Line + 3600 1650 3650 1650 +$Comp +L GND #PWR010 +U 1 1 69B525FF +P 2700 1300 +F 0 "#PWR010" H 2700 1050 50 0001 C CNN +F 1 "GND" H 2700 1150 50 0000 C CNN +F 2 "" H 2700 1300 50 0001 C CNN +F 3 "" H 2700 1300 50 0001 C CNN + 1 2700 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7400 2700 8550 2700 +Wire Wire Line + 8550 2700 8550 2650 +Wire Wire Line + 7400 2800 9150 2800 +Wire Wire Line + 7400 2900 9650 2900 +Wire Wire Line + 7400 3000 10100 3000 +Wire Wire Line + 7400 3100 10700 3100 +$Comp +L plot_v1 U4 +U 1 1 69B534CB +P 8550 2850 +F 0 "U4" H 8550 3350 60 0000 C CNN +F 1 "plot_v1" H 8750 3200 60 0000 C CNN +F 2 "" H 8550 2850 60 0000 C CNN +F 3 "" H 8550 2850 60 0000 C CNN + 1 8550 2850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U10 +U 1 1 69B5351A +P 9150 3000 +F 0 "U10" H 9150 3500 60 0000 C CNN +F 1 "plot_v1" H 9350 3350 60 0000 C CNN +F 2 "" H 9150 3000 60 0000 C CNN +F 3 "" H 9150 3000 60 0000 C CNN + 1 9150 3000 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 69B5355B +P 9650 3100 +F 0 "U11" H 9650 3600 60 0000 C CNN +F 1 "plot_v1" H 9850 3450 60 0000 C CNN +F 2 "" H 9650 3100 60 0000 C CNN +F 3 "" H 9650 3100 60 0000 C CNN + 1 9650 3100 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 69B53598 +P 10100 3200 +F 0 "U12" H 10100 3700 60 0000 C CNN +F 1 "plot_v1" H 10300 3550 60 0000 C CNN +F 2 "" H 10100 3200 60 0000 C CNN +F 3 "" H 10100 3200 60 0000 C CNN + 1 10100 3200 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U13 +U 1 1 69B535DB +P 10700 3300 +F 0 "U13" H 10700 3800 60 0000 C CNN +F 1 "plot_v1" H 10900 3650 60 0000 C CNN +F 2 "" H 10700 3300 60 0000 C CNN +F 3 "" H 10700 3300 60 0000 C CNN + 1 10700 3300 + 1 0 0 -1 +$EndComp +Text Label 7400 2500 0 60 ~ 0 +OUT_1 +Text Label 7550 2600 0 60 ~ 0 +OUT_2 +Text Label 7550 2700 0 60 ~ 0 +OUT_3 +Text Label 7600 2800 0 60 ~ 0 +OUT_4 +Text Label 7650 2900 0 60 ~ 0 +OUT_5 +Text Label 7750 3000 0 60 ~ 0 +OUT_6 +Text Label 7850 3100 0 60 ~ 0 +OUT_7 +Text Label 7700 3200 0 60 ~ 0 +OUT_8 +$EndSCHEMATC diff --git a/hamecc135/README.md.txt b/hamecc135/README.md.txt new file mode 100644 index 0000000..34af2ec --- /dev/null +++ b/hamecc135/README.md.txt @@ -0,0 +1,16 @@ +# hamecc135 - Pipelined Hamming (7,4) Error Correction Core + +## Description +A Pipelined Hamming (7,4) Error Correction Code (ECC) IP core designed for fault-tolerant architectures. Operating across three distinct synchronous stages, the core identifies and strictly corrects single-bit physical channel errors in real-time utilizing a purely Boolean XOR toggling logic engine. + +## Block Diagram +Refer to the comprehensive project report for detailed schematics and block diagrams. + +## Pin Configuration +* **Inputs (13):** clk (1), rst (1), data_in (4), error_inject (7) +* **Outputs (5):** data_out (4), error_detected (1) + +## Author & Contact +* **Name:** Hanzala Zafar +* **Institution:** Jamia Millia Islamia +* **GitHub:** [@zafarhanzala](https://github.com/zafarhanzala) \ No newline at end of file diff --git a/hamecc135/Verilog_Files/hamming_ecc.v b/hamecc135/Verilog_Files/hamming_ecc.v new file mode 100644 index 0000000..1ffad76 --- /dev/null +++ b/hamecc135/Verilog_Files/hamming_ecc.v @@ -0,0 +1,75 @@ +module hamming_ecc ( + input clk, + input rst, + input [3:0] data_in, + input [6:0] error_inject, + output reg [3:0] data_out, + output reg error_detected +); + + reg [6:0] stage1_encoded; + reg [6:0] stage1_err; + + reg [6:0] stage2_rx; + reg [2:0] stage2_syndrome; + + wire p1, p2, p3; + wire s1, s2, s3; + wire [6:0] channel_data; + + // Stage 1: Combinational Parity Generation + assign p1 = data_in[0] ^ data_in[1] ^ data_in[3]; + assign p2 = data_in[0] ^ data_in[2] ^ data_in[3]; + assign p3 = data_in[1] ^ data_in[2] ^ data_in[3]; + + always @(posedge clk or posedge rst) begin + if (rst) begin + stage1_encoded <= 7'd0; + stage1_err <= 7'd0; + end else begin + stage1_encoded <= {data_in[3], data_in[2], data_in[1], p3, data_in[0], p2, p1}; + stage1_err <= error_inject; + end + end + + // The Channel (Error Injection) + assign channel_data = stage1_encoded ^ stage1_err; + + // Stage 2: Combinational Syndrome Calculation + assign s1 = channel_data[0] ^ channel_data[2] ^ channel_data[4] ^ channel_data[6]; + assign s2 = channel_data[1] ^ channel_data[2] ^ channel_data[5] ^ channel_data[6]; + assign s3 = channel_data[3] ^ channel_data[4] ^ channel_data[5] ^ channel_data[6]; + + always @(posedge clk or posedge rst) begin + if (rst) begin + stage2_rx <= 7'd0; + stage2_syndrome <= 3'd0; + end else begin + stage2_rx <= channel_data; + stage2_syndrome <= {s3, s2, s1}; + end + end + + // Stage 3: The Bug-Proof Correction Logic + // If the syndrome matches the bit's error location, the wire goes High (1) + wire flip_d0 = (stage2_syndrome == 3'd3); + wire flip_d1 = (stage2_syndrome == 3'd5); + wire flip_d2 = (stage2_syndrome == 3'd6); + wire flip_d3 = (stage2_syndrome == 3'd7); + + always @(posedge clk or posedge rst) begin + if (rst) begin + data_out <= 4'd0; + error_detected <= 1'b0; + end else begin + error_detected <= (stage2_syndrome != 3'd0); + + // XORing the received bit with the flip wire corrects the error + data_out[0] <= stage2_rx[2] ^ flip_d0; + data_out[1] <= stage2_rx[4] ^ flip_d1; + data_out[2] <= stage2_rx[5] ^ flip_d2; + data_out[3] <= stage2_rx[6] ^ flip_d3; + end + end + +endmodule \ No newline at end of file diff --git a/hamecc135/eSim_Project_Files/hamming_ecc_sub.cir b/hamecc135/eSim_Project_Files/hamming_ecc_sub.cir new file mode 100644 index 0000000..6c0ec95 --- /dev/null +++ b/hamecc135/eSim_Project_Files/hamming_ecc_sub.cir @@ -0,0 +1,6 @@ +.title KiCad schematic +U3 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U3-Pad14_ Net-_U3-Pad15_ Net-_U3-Pad16_ Net-_U3-Pad17_ Net-_U3-Pad18_ hamming_ecc +U4 Net-_U3-Pad14_ Net-_U3-Pad15_ Net-_U3-Pad16_ Net-_U3-Pad17_ Net-_U3-Pad18_ /data_out3 /data_out2 /data_out1 /data_out0 /error_detected0 dac_bridge_5 +U2 /error_inject4 /error_inject3 /error_inject2 /error_inject1 /error_inject0 Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ adc_bridge_5 +U1 /clk /rst /data_in3 /data_in2 /data_in1 /data_in0 /error_inject6 /error_inject5 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ adc_bridge_8 +.end diff --git a/hamecc135/eSim_Project_Files/hamming_ecc_sub.cir.out b/hamecc135/eSim_Project_Files/hamming_ecc_sub.cir.out new file mode 100644 index 0000000..4b6d9ea --- /dev/null +++ b/hamecc135/eSim_Project_Files/hamming_ecc_sub.cir.out @@ -0,0 +1,27 @@ +.title kicad schematic + +* u3 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ net-_u3-pad17_ net-_u3-pad18_ hamming_ecc +* u4 net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ net-_u3-pad17_ net-_u3-pad18_ /data_out3 /data_out2 /data_out1 /data_out0 /error_detected0 dac_bridge_5 +* u2 /error_inject4 /error_inject3 /error_inject2 /error_inject1 /error_inject0 net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ adc_bridge_5 +* u1 /clk /rst /data_in3 /data_in2 /data_in1 /data_in0 /error_inject6 /error_inject5 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ adc_bridge_8 +a1 [net-_u1-pad9_ ] [net-_u1-pad10_ ] [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] [net-_u1-pad15_ net-_u1-pad16_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ ] [net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ net-_u3-pad17_ ] [net-_u3-pad18_ ] u3 +a2 [net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ net-_u3-pad17_ net-_u3-pad18_ ] [/data_out3 /data_out2 /data_out1 /data_out0 /error_detected0 ] u4 +a3 [/error_inject4 /error_inject3 /error_inject2 /error_inject1 /error_inject0 ] [net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ ] u2 +a4 [/clk /rst /data_in3 /data_in2 /data_in1 /data_in0 /error_inject6 /error_inject5 ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ ] u1 +* Schematic Name: hamming_ecc, Ngspice Name: hamming_ecc +.model u3 hamming_ecc(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: dac_bridge_5, Ngspice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_5, Ngspice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_8, Ngspice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/hamecc135/eSim_Project_Files/hamming_ecc_sub.kicad_sch b/hamecc135/eSim_Project_Files/hamming_ecc_sub.kicad_sch new file mode 100644 index 0000000..2e3500f --- /dev/null +++ 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b/hamecc135/eSim_Project_Files/hamming_ecc_sub.sub new file mode 100644 index 0000000..8e82c6a --- /dev/null +++ b/hamecc135/eSim_Project_Files/hamming_ecc_sub.sub @@ -0,0 +1,19 @@ +* --- Pipelined Hamming ECC Subcircuit --- + +.subckt hamming_ecc_sub clk rst data_in3 data_in2 data_in1 data_in0 err6 err5 err4 err3 err2 err1 err0 data_out3 data_out2 data_out1 data_out0 err_det + +* --- ADC Bridges (13 Inputs) --- +A_adc_inputs [clk rst data_in3 data_in2 data_in1 data_in0 err6 err5 err4 err3 err2 err1 err0] [d_clk d_rst d_in3 d_in2 d_in1 d_in0 d_e6 d_e5 d_e4 d_e3 d_e2 d_e1 d_e0] adc_1 + +* --- Verilog Digital Core --- +A_hamming_core [d_clk] [d_rst] [d_in3 d_in2 d_in1 d_in0] [d_e6 d_e5 d_e4 d_e3 d_e2 d_e1 d_e0] [d_out3 d_out2 d_out1 d_out0] [d_err_det] hamming_ecc + +* --- DAC Bridges (5 Outputs) --- +A_dac_outputs [d_out3 d_out2 d_out1 d_out0 d_err_det] [data_out3 data_out2 data_out1 data_out0 err_det] dac_1 + +* --- Standard Bridge Models --- +.model adc_1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9) +.model dac_1 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9) +.model hamming_ecc hamming_ecc(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12) + +.ends hamming_ecc_sub \ No newline at end of file diff --git a/hamecc135/eSim_Project_Files/hamming_ecc_tb.cir b/hamecc135/eSim_Project_Files/hamming_ecc_tb.cir new file mode 100644 index 0000000..a1eecf3 --- /dev/null +++ b/hamecc135/eSim_Project_Files/hamming_ecc_tb.cir @@ -0,0 +1,12 @@ +.title KiCad schematic +v1 /clk GND pulse +v2 /rst GND pulse +v3 /error_inject2 GND pulse +I1 GND Net-_I1-Pad2_ dc +X1 /clk /rst Net-_I1-Pad2_ GND Net-_I1-Pad2_ Net-_I1-Pad2_ GND GND GND GND /error_inject2 GND GND Net-_X1-Pad14_ Net-_X1-Pad15_ Net-_X1-Pad16_ /data_out0 /error_detected hamming_ecc_sub +U3 Net-_X1-Pad15_ plot_v1 +U2 Net-_X1-Pad14_ plot_v1 +U4 Net-_X1-Pad16_ plot_v1 +U5 /data_out0 plot_v1 +U6 /error_detected plot_v1 +.end diff --git a/hamecc135/eSim_Project_Files/hamming_ecc_tb.cir.out b/hamecc135/eSim_Project_Files/hamming_ecc_tb.cir.out new file mode 100644 index 0000000..1d665ae --- /dev/null +++ b/hamecc135/eSim_Project_Files/hamming_ecc_tb.cir.out @@ -0,0 +1,27 @@ +.title kicad schematic + +.include hamming_ecc_sub.sub +v1 /clk gnd pulse(0 5 0 1n 1n 490n 1u) +v2 /rst gnd pulse(5 0 2u 1n 1n 100m 100m) +v3 /error_inject2 gnd pulse(0 5 5u 1n 1n 2500u 8u) +i1 gnd net-_i1-pad2_ dc 5 +x1 /clk /rst net-_i1-pad2_ gnd net-_i1-pad2_ net-_i1-pad2_ gnd gnd gnd gnd /error_inject2 gnd gnd net-_x1-pad14_ net-_x1-pad15_ net-_x1-pad16_ /data_out0 /error_detected hamming_ecc_sub +* u3 net-_x1-pad15_ plot_v1 +* u2 net-_x1-pad14_ plot_v1 +* u4 net-_x1-pad16_ plot_v1 +* u5 /data_out0 plot_v1 +* u6 /error_detected plot_v1 +.tran 10e-09 20e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(net-_x1-pad15_) +plot v(net-_x1-pad14_) +plot v(net-_x1-pad16_) +plot v(/data_out0) +plot v(/error_detected) +.endc +.end diff --git a/hamecc135/eSim_Project_Files/hamming_ecc_tb.kicad_sch b/hamecc135/eSim_Project_Files/hamming_ecc_tb.kicad_sch new file mode 100644 index 0000000..1853899 --- /dev/null +++ b/hamecc135/eSim_Project_Files/hamming_ecc_tb.kicad_sch @@ -0,0 +1,818 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 2d0817aa-6c76-4d84-a773-2d55200c41b7) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Plot:plot_v1" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 12.7 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "plot_v1" (id 1) (at 5.08 8.89 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "plot_v1_0_1" + (circle (center 0 12.7) (radius 2.54) + (stroke (width 0) (type default) (color 0 0 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The architecture incorporates the strict 1-bit delay constraint required for proper Word Select (WS/LRCLK) protocol alignment in digital audio devices. + +## Block Diagram +Refer to the comprehensive project report for detailed schematics and block diagrams. + +## Pin Configuration +* **Inputs (35):** clk (1), rst (1), lrclk (1), left_data (16), right_data (16) +* **Outputs (1):** sdata (1) + +## Author & Contact +* **Name:** Hanzala Zafar +* **Institution:** Jamia Millia Islamia +* **GitHub:** [@zafarhanzala](https://github.com/zafarhanzala) \ No newline at end of file diff --git a/i2stx351/Verilog_Files/i2s_tx_16bit.v b/i2stx351/Verilog_Files/i2s_tx_16bit.v new file mode 100644 index 0000000..ae22137 --- /dev/null +++ b/i2stx351/Verilog_Files/i2s_tx_16bit.v @@ -0,0 +1,38 @@ +module i2s_tx_16bit ( + input bclk, + input rst, + input [15:0] left_data, + input [15:0] right_data, + output reg lrclk, + output reg sdata +); + + reg [4:0] bit_counter; + reg [31:0] shift_reg; + + always @(posedge bclk or posedge rst) begin + if (rst) begin + bit_counter <= 5'd0; + lrclk <= 1'b0; + sdata <= 1'b0; + shift_reg <= 32'd0; + end else begin + + bit_counter <= bit_counter + 1'b1; + + if (bit_counter == 5'd15) + lrclk <= 1'b1; + else if (bit_counter == 5'd31) + lrclk <= 1'b0; + + if (bit_counter == 5'd0) begin + shift_reg <= {left_data, right_data}; + end else begin + shift_reg <= {shift_reg[30:0], 1'b0}; + end + + sdata <= shift_reg[31]; + end + end + +endmodule \ No newline at end of file diff --git a/i2stx351/eSim_Project_Files/I2Ssub.cir b/i2stx351/eSim_Project_Files/I2Ssub.cir new file mode 100644 index 0000000..1816242 --- /dev/null +++ b/i2stx351/eSim_Project_Files/I2Ssub.cir @@ -0,0 +1,9 @@ +.title KiCad schematic +U5 /left_data1 /left_data0 /right_data15 /right_data14 /right_data13 /right_data12 /right_data11 /right_data10 Net-_U5-Pad9_ Net-_U5-Pad10_ Net-_U5-Pad11_ Net-_U5-Pad12_ Net-_U5-Pad13_ Net-_U5-Pad14_ Net-_U5-Pad15_ Net-_U5-Pad16_ adc_bridge_8 +U6 Net-_U3-Pad9_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U3-Pad12_ Net-_U3-Pad13_ Net-_U3-Pad14_ Net-_U3-Pad15_ Net-_U3-Pad16_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U5-Pad9_ Net-_U5-Pad10_ Net-_U5-Pad11_ Net-_U5-Pad12_ Net-_U5-Pad13_ Net-_U5-Pad14_ Net-_U5-Pad15_ Net-_U5-Pad16_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U4-Pad3_ Net-_U4-Pad4_ Net-_U6-Pad35_ Net-_U6-Pad36_ i2s_tx_16bit +U7 Net-_U6-Pad35_ Net-_U6-Pad36_ /lrclk /sdata dac_bridge_2 +U3 /bclk /rst /left_data15 /left_data14 /left_data13 /left_data12 /left_data11 /left_data10 Net-_U3-Pad9_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U3-Pad12_ Net-_U3-Pad13_ Net-_U3-Pad14_ Net-_U3-Pad15_ Net-_U3-Pad16_ adc_bridge_8 +U1 /left_data9 /left_data8 /left_data7 /left_data6 /left_data5 /left_data4 /left_data3 /left_data2 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ adc_bridge_8 +U4 /right_data1 /right_data0 Net-_U4-Pad3_ Net-_U4-Pad4_ adc_bridge_2 +U2 /right_data9 /right_data8 /right_data7 /right_data6 /right_data5 /right_data4 /right_data3 /right_data2 Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ adc_bridge_8 +.end diff --git a/i2stx351/eSim_Project_Files/I2Ssub.cir.out b/i2stx351/eSim_Project_Files/I2Ssub.cir.out new file mode 100644 index 0000000..c3a349e --- /dev/null +++ b/i2stx351/eSim_Project_Files/I2Ssub.cir.out @@ -0,0 +1,39 @@ +.title kicad schematic + +* u5 /left_data1 /left_data0 /right_data15 /right_data14 /right_data13 /right_data12 /right_data11 /right_data10 net-_u5-pad9_ net-_u5-pad10_ net-_u5-pad11_ net-_u5-pad12_ net-_u5-pad13_ net-_u5-pad14_ net-_u5-pad15_ net-_u5-pad16_ adc_bridge_8 +* u6 net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u5-pad9_ net-_u5-pad10_ net-_u5-pad11_ net-_u5-pad12_ net-_u5-pad13_ net-_u5-pad14_ net-_u5-pad15_ net-_u5-pad16_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u4-pad3_ net-_u4-pad4_ net-_u6-pad35_ net-_u6-pad36_ i2s_tx_16bit +* u7 net-_u6-pad35_ net-_u6-pad36_ /lrclk /sdata dac_bridge_2 +* u3 /bclk /rst /left_data15 /left_data14 /left_data13 /left_data12 /left_data11 /left_data10 net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ adc_bridge_8 +* u1 /left_data9 /left_data8 /left_data7 /left_data6 /left_data5 /left_data4 /left_data3 /left_data2 net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ adc_bridge_8 +* u4 /right_data1 /right_data0 net-_u4-pad3_ net-_u4-pad4_ adc_bridge_2 +* u2 /right_data9 /right_data8 /right_data7 /right_data6 /right_data5 /right_data4 /right_data3 /right_data2 net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8 +a1 [/left_data1 /left_data0 /right_data15 /right_data14 /right_data13 /right_data12 /right_data11 /right_data10 ] [net-_u5-pad9_ net-_u5-pad10_ net-_u5-pad11_ net-_u5-pad12_ net-_u5-pad13_ net-_u5-pad14_ net-_u5-pad15_ net-_u5-pad16_ ] u5 +a2 [net-_u3-pad9_ ] [net-_u3-pad10_ ] [net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u5-pad9_ net-_u5-pad10_ ] [net-_u5-pad11_ net-_u5-pad12_ net-_u5-pad13_ net-_u5-pad14_ net-_u5-pad15_ net-_u5-pad16_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u4-pad3_ net-_u4-pad4_ ] [net-_u6-pad35_ ] [net-_u6-pad36_ ] u6 +a3 [net-_u6-pad35_ net-_u6-pad36_ ] [/lrclk /sdata ] u7 +a4 [/bclk /rst /left_data15 /left_data14 /left_data13 /left_data12 /left_data11 /left_data10 ] [net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ ] u3 +a5 [/left_data9 /left_data8 /left_data7 /left_data6 /left_data5 /left_data4 /left_data3 /left_data2 ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ ] u1 +a6 [/right_data1 /right_data0 ] [net-_u4-pad3_ net-_u4-pad4_ ] u4 +a7 [/right_data9 /right_data8 /right_data7 /right_data6 /right_data5 /right_data4 /right_data3 /right_data2 ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2 +* Schematic Name: adc_bridge_8, Ngspice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: i2s_tx_16bit, Ngspice Name: i2s_tx_16bit +.model u6 i2s_tx_16bit(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: dac_bridge_2, Ngspice Name: dac_bridge +.model u7 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_8, Ngspice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_8, Ngspice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, Ngspice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_8, Ngspice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/i2stx351/eSim_Project_Files/I2Ssub.kicad_sch b/i2stx351/eSim_Project_Files/I2Ssub.kicad_sch new file mode 100644 index 0000000..73be16e --- /dev/null +++ b/i2stx351/eSim_Project_Files/I2Ssub.kicad_sch @@ -0,0 +1,1035 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid d52c87e2-8cc6-4675-88fe-a7e115c6e2a4) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Hybrid:adc_bridge_2" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "adc_bridge_2" (id 1) (at 0 3.81 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "adc_bridge_2_0_1" + (rectangle (start -10.16 5.08) (end 8.89 -2.54) + (stroke (width 0) (type default) (color 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+A_adc_clk [bclk] [d_bclk] adc_1 +A_adc_rst [rst] [d_rst] adc_1 + +* --- ADC Bridges (Left Channel 16-bit) --- +A_adc_left [left15 left14 left13 left12 left11 left10 left9 left8 left7 left6 left5 left4 left3 left2 left1 left0] [d_l15 d_l14 d_l13 d_l12 d_l11 d_l10 d_l9 d_l8 d_l7 d_l6 d_l5 d_l4 d_l3 d_l2 d_l1 d_l0] adc_1 + +* --- ADC Bridges (Right Channel 16-bit) --- +A_adc_right [right15 right14 right13 right12 right11 right10 right9 right8 right7 right6 right5 right4 right3 right2 right1 right0] [d_r15 d_r14 d_r13 d_r12 d_r11 d_r10 d_r9 d_r8 d_r7 d_r6 d_r5 d_r4 d_r3 d_r2 d_r1 d_r0] adc_1 + +* --- Verilog Digital Core --- +A_i2s_core [d_bclk] [d_rst] [d_l15 d_l14 d_l13 d_l12 d_l11 d_l10 d_l9 d_l8 d_l7 d_l6 d_l5 d_l4 d_l3 d_l2 d_l1 d_l0] [d_r15 d_r14 d_r13 d_r12 d_r11 d_r10 d_r9 d_r8 d_r7 d_r6 d_r5 d_r4 d_r3 d_r2 d_r1 d_r0] [d_lrclk] [d_sdata] i2s_tx_16bit + +* --- DAC Bridges (Outputs) --- +A_dac_lrclk [d_lrclk] [lrclk] dac_1 +A_dac_sdata [d_sdata] [sdata] dac_1 + +* --- Standard Bridge Models --- +.model adc_1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9) +.model dac_1 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9) +.model i2s_tx_16bit i2s_tx_16bit(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12) + +.ends I2Ssub \ No newline at end of file diff --git a/i2stx351/eSim_Project_Files/I2Stb.cir b/i2stx351/eSim_Project_Files/I2Stb.cir new file mode 100644 index 0000000..f521e94 --- /dev/null +++ b/i2stx351/eSim_Project_Files/I2Stb.cir @@ -0,0 +1,8 @@ +.title KiCad schematic +I1 /VDD_5V GND dc +v1 /bclk_label GND pulse +v2 /rst_label GND pulse +X1 /bclk_label /rst_label /VDD_5V GND /VDD_5V GND /VDD_5V GND /VDD_5V GND /VDD_5V GND /VDD_5V GND /VDD_5V GND /VDD_5V GND /VDD_5V /VDD_5V /VDD_5V /VDD_5V GND GND GND GND /VDD_5V /VDD_5V /VDD_5V /VDD_5V GND GND GND GND /lrclk_label /sdata_label I2Ssub +U2 /sdata_label plot_v1 +U1 /lrclk_label plot_v1 +.end diff --git a/i2stx351/eSim_Project_Files/I2Stb.cir.out b/i2stx351/eSim_Project_Files/I2Stb.cir.out new file mode 100644 index 0000000..d921e9b --- /dev/null +++ b/i2stx351/eSim_Project_Files/I2Stb.cir.out @@ -0,0 +1,20 @@ +.title kicad schematic + +.include I2Ssub.sub +i1 /vdd_5v gnd dc -5 +v1 /bclk_label gnd pulse(0 5 0 1n 1n 49n 100n) +v2 /rst_label gnd pulse(5 0 150n 1n 1n 1000m 1000m) +x1 /bclk_label /rst_label /vdd_5v gnd /vdd_5v gnd /vdd_5v gnd /vdd_5v gnd /vdd_5v gnd /vdd_5v gnd /vdd_5v gnd /vdd_5v gnd /vdd_5v /vdd_5v /vdd_5v /vdd_5v gnd gnd gnd gnd /vdd_5v /vdd_5v /vdd_5v /vdd_5v gnd gnd gnd gnd /lrclk_label /sdata_label I2Ssub +* u2 /sdata_label plot_v1 +* u1 /lrclk_label plot_v1 +.tran 10e-09 10e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(/sdata_label) +plot v(/lrclk_label) +.endc +.end diff --git a/i2stx351/eSim_Project_Files/I2Stb.kicad_sch b/i2stx351/eSim_Project_Files/I2Stb.kicad_sch new file mode 100644 index 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Processing (DSP). This synchronous RTL module multiplies two 4-bit input buses and continuously accumulates the product over multiple clock cycles into an 8-bit register, featuring internal overflow detection. + +## Block Diagram +Refer to the comprehensive project report for detailed schematics and block diagrams. + +## Pin Configuration +* **Inputs (12):** clk (1), reset (1), enable (1), clr_accum (1), data_a (4), data_b (4) +* **Outputs (9):** accum_out (8), overflow_flag (1) + +## Author & Contact +* **Name:** Hanzala Zafar +* **Institution:** Jamia Millia Islamia +* **GitHub:** [@zafarhanzala](https://github.com/zafarhanzala) \ No newline at end of file diff --git a/mac129/Verilog_Files/mac_unit.v b/mac129/Verilog_Files/mac_unit.v new file mode 100644 index 0000000..659f0f3 --- /dev/null +++ b/mac129/Verilog_Files/mac_unit.v @@ -0,0 +1,35 @@ +/* Single-Block MAC Unit for eSim Mixed-Signal Simulation */ +module mac_unit ( + input wire clk, + input wire reset, + input wire enable, + input wire clr_accum, // Pulse high to reset accumulator to 0 before a new operation + input wire [3:0] data_a, // 4-bit multiplicand + input wire [3:0] data_b, // 4-bit multiplier + output reg [7:0] accum_out, // 8-bit accumulated result + output reg overflow_flag // Goes high if addition exceeds 8 bits +); + + reg [7:0] product; + reg [8:0] temp_accum; // 9 bits internally to catch overflow + + always @(posedge clk or posedge reset) begin + if (reset) begin + accum_out <= 8'd0; + overflow_flag <= 1'b0; + end else if (enable) begin + product = data_a * data_b; // Combinational multiplication + + if (clr_accum) begin + // Start a new sequence: just store the product, don't add to old data + accum_out <= product; + overflow_flag <= 1'b0; + end else begin + // Accumulate: add new product to existing total + temp_accum = accum_out + product; + accum_out <= temp_accum[7:0]; + overflow_flag <= temp_accum[8]; + end + end + end +endmodule \ No newline at end of file diff --git a/mac129/eSim_Project_Files/MACProject-cache.lib b/mac129/eSim_Project_Files/MACProject-cache.lib new file mode 100644 index 0000000..ad50d0a --- /dev/null +++ b/mac129/eSim_Project_Files/MACProject-cache.lib @@ -0,0 +1,162 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_8 +# +DEF dac_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# mac_unit +# +DEF mac_unit U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "mac_unit" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 600 0 1 0 N +X clk0 1 2150 1900 200 R 50 50 1 1 I +X reset0 2 2150 1800 200 R 50 50 1 1 I +X enable0 3 2150 1700 200 R 50 50 1 1 I +X clr_accum0 4 2150 1600 200 R 50 50 1 1 I +X data_a3 5 2150 1500 200 R 50 50 1 1 I +X data_a2 6 2150 1400 200 R 50 50 1 1 I +X data_a1 7 2150 1300 200 R 50 50 1 1 I +X data_a0 8 2150 1200 200 R 50 50 1 1 I +X data_b3 9 2150 1100 200 R 50 50 1 1 I +X data_b2 10 2150 1000 200 R 50 50 1 1 I +X accum_out0 20 3550 1200 200 L 50 50 1 1 O +X data_b1 11 2150 900 200 R 50 50 1 1 I +X overflow_flag0 21 3550 1100 200 L 50 50 1 1 O +X data_b0 12 2150 800 200 R 50 50 1 1 I +X accum_out7 13 3550 1900 200 L 50 50 1 1 O +X accum_out6 14 3550 1800 200 L 50 50 1 1 O +X accum_out5 15 3550 1700 200 L 50 50 1 1 O +X accum_out4 16 3550 1600 200 L 50 50 1 1 O +X accum_out3 17 3550 1500 200 L 50 50 1 1 O +X accum_out2 18 3550 1400 200 L 50 50 1 1 O +X accum_out1 19 3550 1300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/mac129/eSim_Project_Files/MACProject.bak b/mac129/eSim_Project_Files/MACProject.bak new file mode 100644 index 0000000..2fa3abc --- /dev/null +++ b/mac129/eSim_Project_Files/MACProject.bak @@ -0,0 +1,571 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul 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3200 4850 60 0000 C CNN +F 2 "" H 3200 4550 60 0000 C CNN +F 3 "" H 3200 4550 60 0000 C CNN + 1 3200 4550 + 0 1 1 0 +$EndComp +$Comp +L dac_bridge_8 U8 +U 1 1 69AAA5D6 +P 5250 2250 +F 0 "U8" H 5250 2250 60 0000 C CNN +F 1 "dac_bridge_8" H 5250 2400 60 0000 C CNN +F 2 "" H 5250 2250 60 0000 C CNN +F 3 "" H 5250 2250 60 0000 C CNN + 1 5250 2250 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U9 +U 1 1 69AAA629 +P 5300 3500 +F 0 "U9" H 5300 3500 60 0000 C CNN +F 1 "dac_bridge_1" H 5300 3650 60 0000 C CNN +F 2 "" H 5300 3500 60 0000 C CNN +F 3 "" H 5300 3500 60 0000 C CNN + 1 5300 3500 + 1 0 0 -1 +$EndComp +$Comp +L pulse v6 +U 1 1 69AAA680 +P 3100 5550 +F 0 "v6" H 2900 5650 60 0000 C CNN +F 1 "pulse" H 2900 5500 60 0000 C CNN +F 2 "R1" H 2800 5550 60 0000 C CNN +F 3 "" H 3100 5550 60 0000 C CNN + 1 3100 5550 + 1 0 0 -1 +$EndComp +$Comp +L pulse v5 +U 1 1 69AAA701 +P 2250 5350 +F 0 "v5" H 2050 5450 60 0000 C CNN +F 1 "pulse" H 2050 5300 60 0000 C CNN +F 2 "R1" H 1950 5350 60 0000 C CNN +F 3 "" H 2250 5350 60 0000 C CNN + 1 2250 5350 + 1 0 0 -1 +$EndComp +$Comp +L pulse v3 +U 1 1 69AAA74A +P 1350 3350 +F 0 "v3" H 1150 3450 60 0000 C CNN +F 1 "pulse" H 1150 3300 60 0000 C CNN +F 2 "R1" H 1050 3350 60 0000 C CNN +F 3 "" H 1350 3350 60 0000 C CNN + 1 1350 3350 + 1 0 0 -1 +$EndComp +$Comp +L pulse v2 +U 1 1 69AAA80D +P 1000 2950 +F 0 "v2" H 800 3050 60 0000 C CNN +F 1 "pulse" H 800 2900 60 0000 C CNN +F 2 "R1" H 700 2950 60 0000 C CNN +F 3 "" H 1000 2950 60 0000 C CNN + 1 1000 2950 + 1 0 0 -1 +$EndComp +$Comp +L pulse v1 +U 1 1 69AAA878 +P 800 2400 +F 0 "v1" H 600 2500 60 0000 C CNN +F 1 "pulse" H 600 2350 60 0000 C CNN +F 2 "R1" H 500 2400 60 0000 C CNN +F 3 "" H 800 2400 60 0000 C CNN + 1 800 2400 + 1 0 0 -1 +$EndComp +$Comp +L pulse v4 +U 1 1 69AAA8BB +P 1600 1400 +F 0 "v4" H 1400 1500 60 0000 C CNN +F 1 "pulse" H 1400 1350 60 0000 C CNN +F 2 "R1" H 1300 1400 60 0000 C CNN +F 3 "" H 1600 1400 60 0000 C CNN + 1 1600 1400 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR10 +U 1 1 69AAAA0D +P 3200 5100 +F 0 "#PWR10" H 3200 4850 50 0001 C CNN +F 1 "GND" H 3200 4950 50 0000 C CNN +F 2 "" H 3200 5100 50 0001 C CNN +F 3 "" H 3200 5100 50 0001 C CNN + 1 3200 5100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR11 +U 1 1 69AAAA99 +P 3300 5100 +F 0 "#PWR11" H 3300 4850 50 0001 C CNN +F 1 "GND" H 3300 4950 50 0000 C CNN +F 2 "" H 3300 5100 50 0001 C CNN +F 3 "" H 3300 5100 50 0001 C CNN + 1 3300 5100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR12 +U 1 1 69AAAACB +P 3400 5100 +F 0 "#PWR12" H 3400 4850 50 0001 C CNN +F 1 "GND" H 3400 4950 50 0000 C CNN +F 2 "" H 3400 5100 50 0001 C CNN +F 3 "" H 3400 5100 50 0001 C CNN + 1 3400 5100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR9 +U 1 1 69AAAAFD +P 3100 6000 +F 0 "#PWR9" H 3100 5750 50 0001 C CNN +F 1 "GND" H 3100 5850 50 0000 C CNN +F 2 "" H 3100 6000 50 0001 C CNN +F 3 "" H 3100 6000 50 0001 C CNN + 1 3100 6000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR5 +U 1 1 69AAAB2F +P 2250 5800 +F 0 "#PWR5" H 2250 5550 50 0001 C CNN +F 1 "GND" H 2250 5650 50 0000 C CNN +F 2 "" H 2250 5800 50 0001 C CNN +F 3 "" H 2250 5800 50 0001 C CNN + 1 2250 5800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR6 +U 1 1 69AAAB61 +P 2350 4900 +F 0 "#PWR6" H 2350 4650 50 0001 C CNN +F 1 "GND" H 2350 4750 50 0000 C CNN +F 2 "" H 2350 4900 50 0001 C CNN +F 3 "" H 2350 4900 50 0001 C CNN + 1 2350 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR7 +U 1 1 69AAAB93 +P 2450 4900 +F 0 "#PWR7" H 2450 4650 50 0001 C CNN +F 1 "GND" H 2450 4750 50 0000 C CNN +F 2 "" H 2450 4900 50 0001 C CNN +F 3 "" H 2450 4900 50 0001 C CNN + 1 2450 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR8 +U 1 1 69AAABC5 +P 2550 4900 +F 0 "#PWR8" H 2550 4650 50 0001 C CNN +F 1 "GND" H 2550 4750 50 0000 C CNN +F 2 "" H 2550 4900 50 0001 C CNN +F 3 "" H 2550 4900 50 0001 C CNN + 1 2550 4900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR4 +U 1 1 69AAAC24 +P 1350 3800 +F 0 "#PWR4" H 1350 3550 50 0001 C CNN +F 1 "GND" H 1350 3650 50 0000 C CNN +F 2 "" H 1350 3800 50 0001 C CNN +F 3 "" H 1350 3800 50 0001 C CNN + 1 1350 3800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR2 +U 1 1 69AAAD0A +P 1000 3400 +F 0 "#PWR2" H 1000 3150 50 0001 C CNN +F 1 "GND" H 1000 3250 50 0000 C CNN +F 2 "" H 1000 3400 50 0001 C CNN +F 3 "" H 1000 3400 50 0001 C CNN + 1 1000 3400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 69AAAD3C +P 800 2850 +F 0 "#PWR1" H 800 2600 50 0001 C CNN +F 1 "GND" H 800 2700 50 0000 C CNN +F 2 "" H 800 2850 50 0001 C CNN +F 3 "" H 800 2850 50 0001 C CNN + 1 800 2850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR3 +U 1 1 69AAAD6E +P 1150 1400 +F 0 "#PWR3" H 1150 1150 50 0001 C CNN +F 1 "GND" H 1150 1250 50 0000 C CNN +F 2 "" H 1150 1400 50 0001 C CNN +F 3 "" H 1150 1400 50 0001 C CNN + 1 1150 1400 + 1 0 0 -1 +$EndComp +Text Label 5850 3450 0 60 ~ 0 +OVERFLOW +Text Label 5800 2200 0 60 ~ 0 +OUT_1 +Text Label 5800 2300 0 60 ~ 0 +OUT_2 +Text Label 5800 2400 0 60 ~ 0 +OUT_3 +Text Label 5800 2500 0 60 ~ 0 +OUT_4 +Text Label 5800 2600 0 60 ~ 0 +OUT_5 +Text Label 5800 2700 0 60 ~ 0 +OUT_6 +Text Label 5800 2800 0 60 ~ 0 +OUT_7 +Text Label 5800 2900 0 60 ~ 0 +OUT_8 +Wire Wire Line + 3250 3300 3250 3750 +Wire Wire Line + 3250 3750 3400 3750 +Wire Wire Line + 3400 3750 3400 4000 +Wire Wire Line + 3250 3200 3150 3200 +Wire Wire Line + 3150 3200 3150 3800 +Wire Wire Line + 3150 3800 3300 3800 +Wire Wire Line + 3300 3800 3300 4000 +Wire Wire Line + 3250 3100 3100 3100 +Wire Wire Line + 3100 3100 3100 3850 +Wire Wire Line + 3100 3850 3200 3850 +Wire Wire Line + 3200 3850 3200 4000 +Wire Wire Line + 3250 3000 3050 3000 +Wire Wire Line + 3050 3000 3050 4000 +Wire Wire Line + 3050 4000 3100 4000 +Wire Wire Line + 3200 1400 3200 2200 +Wire Wire Line + 3200 2200 3250 2200 +Wire Wire Line + 3250 2300 2200 2300 +Wire Wire Line + 2200 2300 2200 1950 +Wire Wire Line + 3250 2400 2250 2400 +Wire Wire Line + 2250 2400 2250 2500 +Wire Wire Line + 3250 2500 2500 2500 +Wire Wire Line + 2500 2500 2500 2900 +Wire Wire Line + 3250 2900 2900 2900 +Wire Wire Line + 2900 2900 2900 3800 +Wire Wire Line + 2900 3800 2550 3800 +Wire Wire Line + 3250 2800 2850 2800 +Wire Wire Line + 2850 2800 2850 3750 +Wire Wire Line + 2850 3750 2450 3750 +Wire Wire Line + 2450 3750 2450 3800 +Wire Wire Line + 3250 2700 2800 2700 +Wire Wire Line + 2800 2700 2800 3700 +Wire Wire Line + 2800 3700 2350 3700 +Wire Wire Line + 2350 3700 2350 3800 +Wire Wire Line + 3250 2600 2750 2600 +Wire Wire Line + 2750 2600 2750 3650 +Wire Wire Line + 2750 3650 2250 3650 +Wire Wire Line + 2250 3650 2250 3800 +Wire Wire Line + 1050 1950 800 1950 +Wire Wire Line + 1100 2500 1000 2500 +Wire Wire Line + 4650 3000 4650 3450 +Wire Wire Line + 4650 3450 4700 3450 +Wire Wire Line + 5800 2200 6200 2200 +Wire Wire Line + 5800 2300 6550 2300 +Wire Wire Line + 5800 2400 6950 2400 +Wire Wire Line + 5800 2500 7350 2500 +Wire Wire Line + 5800 2600 7850 2600 +Wire Wire Line + 5800 2700 8350 2700 +Wire Wire Line + 5800 2800 7500 2800 +Wire Wire Line + 5800 2900 6900 2900 +Wire Wire Line + 5850 3450 6550 3450 +$Comp +L plot_v1 U10 +U 1 1 69AACE66 +P 6200 2400 +F 0 "U10" H 6200 2900 60 0000 C CNN +F 1 "plot_v1" H 6400 2750 60 0000 C CNN +F 2 "" H 6200 2400 60 0000 C CNN +F 3 "" H 6200 2400 60 0000 C CNN + 1 6200 2400 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 69AAD09C +P 6550 2500 +F 0 "U12" H 6550 3000 60 0000 C CNN +F 1 "plot_v1" H 6750 2850 60 0000 C CNN +F 2 "" H 6550 2500 60 0000 C CNN +F 3 "" H 6550 2500 60 0000 C CNN + 1 6550 2500 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U14 +U 1 1 69AAD0EB +P 6950 2600 +F 0 "U14" H 6950 3100 60 0000 C CNN +F 1 "plot_v1" H 7150 2950 60 0000 C CNN +F 2 "" H 6950 2600 60 0000 C CNN +F 3 "" H 6950 2600 60 0000 C CNN + 1 6950 2600 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U15 +U 1 1 69AAD136 +P 7350 2700 +F 0 "U15" H 7350 3200 60 0000 C CNN +F 1 "plot_v1" H 7550 3050 60 0000 C CNN +F 2 "" H 7350 2700 60 0000 C CNN +F 3 "" H 7350 2700 60 0000 C CNN + 1 7350 2700 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U17 +U 1 1 69AAD179 +P 7850 2800 +F 0 "U17" H 7850 3300 60 0000 C CNN +F 1 "plot_v1" H 8050 3150 60 0000 C CNN +F 2 "" H 7850 2800 60 0000 C CNN +F 3 "" H 7850 2800 60 0000 C CNN + 1 7850 2800 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U18 +U 1 1 69AAD1C2 +P 8350 2900 +F 0 "U18" H 8350 3400 60 0000 C CNN +F 1 "plot_v1" H 8550 3250 60 0000 C CNN +F 2 "" H 8350 2900 60 0000 C CNN +F 3 "" H 8350 2900 60 0000 C CNN + 1 8350 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U16 +U 1 1 69AAD21D +P 7500 2600 +F 0 "U16" H 7500 3100 60 0000 C CNN +F 1 "plot_v1" H 7700 2950 60 0000 C CNN +F 2 "" H 7500 2600 60 0000 C CNN +F 3 "" H 7500 2600 60 0000 C CNN + 1 7500 2600 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U13 +U 1 1 69AAD27E +P 6900 2700 +F 0 "U13" H 6900 3200 60 0000 C CNN +F 1 "plot_v1" H 7100 3050 60 0000 C CNN +F 2 "" H 6900 2700 60 0000 C CNN +F 3 "" H 6900 2700 60 0000 C CNN + 1 6900 2700 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 69AAD2D7 +P 6350 3450 +F 0 "U11" H 6350 3950 60 0000 C CNN +F 1 "plot_v1" H 6550 3800 60 0000 C CNN +F 2 "" H 6350 3450 60 0000 C CNN +F 3 "" H 6350 3450 60 0000 C CNN + 1 6350 3450 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/mac129/eSim_Project_Files/MACProject.cir b/mac129/eSim_Project_Files/MACProject.cir new file mode 100644 index 0000000..02d03c8 --- /dev/null +++ b/mac129/eSim_Project_Files/MACProject.cir @@ -0,0 +1,34 @@ +* C:\FOSSEE\eSim-Workspace\MACProject\MACProject.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/06/26 18:02:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ mac_unit +U6 Net-_U6-Pad1_ Net-_U1-Pad1_ adc_bridge_1 +U2 Net-_U2-Pad1_ Net-_U1-Pad2_ adc_bridge_1 +U3 Net-_U3-Pad1_ Net-_U1-Pad3_ adc_bridge_1 +U4 Net-_U4-Pad1_ Net-_U1-Pad4_ adc_bridge_1 +U5 Net-_U5-Pad1_ GND GND GND Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ adc_bridge_4 +U7 Net-_U7-Pad1_ GND GND GND Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ adc_bridge_4 +U8 Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ /OUT_1 /OUT_2 /OUT_3 /OUT_4 /OUT_5 /OUT_6 /OUT_7 /OUT_8 dac_bridge_8 +U9 Net-_U1-Pad21_ /OVERFLOW dac_bridge_1 +v6 Net-_U7-Pad1_ GND pulse +v5 Net-_U5-Pad1_ GND pulse +v3 Net-_U4-Pad1_ GND pulse +v2 Net-_U3-Pad1_ GND pulse +v1 Net-_U2-Pad1_ GND pulse +v4 Net-_U6-Pad1_ GND pulse +U10 /OUT_1 plot_v1 +U12 /OUT_2 plot_v1 +U14 /OUT_3 plot_v1 +U15 /OUT_4 plot_v1 +U17 /OUT_5 plot_v1 +U18 /OUT_6 plot_v1 +U16 /OUT_7 plot_v1 +U13 /OUT_8 plot_v1 +U11 /OVERFLOW plot_v1 + +.end diff --git a/mac129/eSim_Project_Files/MACProject.cir.out b/mac129/eSim_Project_Files/MACProject.cir.out new file mode 100644 index 0000000..07beb32 --- /dev/null +++ b/mac129/eSim_Project_Files/MACProject.cir.out @@ -0,0 +1,71 @@ +* c:\fossee\esim-workspace\macproject\macproject.cir + +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ mac_unit +* u6 net-_u6-pad1_ net-_u1-pad1_ adc_bridge_1 +* u2 net-_u2-pad1_ net-_u1-pad2_ adc_bridge_1 +* u3 net-_u3-pad1_ net-_u1-pad3_ adc_bridge_1 +* u4 net-_u4-pad1_ net-_u1-pad4_ adc_bridge_1 +* u5 net-_u5-pad1_ gnd gnd gnd net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ adc_bridge_4 +* u7 net-_u7-pad1_ gnd gnd gnd net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ adc_bridge_4 +* u8 net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ /out_1 /out_2 /out_3 /out_4 /out_5 /out_6 /out_7 /out_8 dac_bridge_8 +* u9 net-_u1-pad21_ /overflow dac_bridge_1 +v6 net-_u7-pad1_ gnd pulse(0 5 0 1u 1u 1000m 1000m) +v5 net-_u5-pad1_ gnd pulse(0 5 0 1u 1u 1000m 1000m) +v3 net-_u4-pad1_ gnd pulse(0 0 0 0 0 0 0) +v2 net-_u3-pad1_ gnd pulse(0 5 3m 1u 1u 1000m 1000m) +v1 net-_u2-pad1_ gnd pulse(5 0 2m 1u 1u 1000m 1000m) +v4 net-_u6-pad1_ gnd pulse(0 5 0 1u 1u 5m 10m) +* u10 /out_1 plot_v1 +* u12 /out_2 plot_v1 +* u14 /out_3 plot_v1 +* u15 /out_4 plot_v1 +* u17 /out_5 plot_v1 +* u18 /out_6 plot_v1 +* u16 /out_7 plot_v1 +* u13 /out_8 plot_v1 +* u11 /overflow plot_v1 +a1 [net-_u1-pad1_ ] [net-_u1-pad2_ ] [net-_u1-pad3_ ] [net-_u1-pad4_ ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ ] [net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ ] [net-_u1-pad21_ ] u1 +a2 [net-_u6-pad1_ ] [net-_u1-pad1_ ] u6 +a3 [net-_u2-pad1_ ] [net-_u1-pad2_ ] u2 +a4 [net-_u3-pad1_ ] [net-_u1-pad3_ ] u3 +a5 [net-_u4-pad1_ ] [net-_u1-pad4_ ] u4 +a6 [net-_u5-pad1_ gnd gnd gnd ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u5 +a7 [net-_u7-pad1_ gnd gnd gnd ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ ] u7 +a8 [net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ ] [/out_1 /out_2 /out_3 /out_4 /out_5 /out_6 /out_7 /out_8 ] u8 +a9 [net-_u1-pad21_ ] [/overflow ] u9 +* Schematic Name: mac_unit, NgSpice Name: mac_unit +.model u1 mac_unit(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 100e-06 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(/out_1) +plot v(/out_2) +plot v(/out_3) +plot v(/out_4) +plot v(/out_5) +plot v(/out_6) +plot v(/out_7) +plot v(/out_8) +plot v(/overflow) +.endc +.end diff --git a/mac129/eSim_Project_Files/MACProject.pro b/mac129/eSim_Project_Files/MACProject.pro new file mode 100644 index 0000000..e27a398 --- /dev/null +++ b/mac129/eSim_Project_Files/MACProject.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/mac129/eSim_Project_Files/MACProject.proj b/mac129/eSim_Project_Files/MACProject.proj new file mode 100644 index 0000000..0446780 --- /dev/null +++ b/mac129/eSim_Project_Files/MACProject.proj @@ -0,0 +1 @@ +schematicFile MACProject.sch diff --git a/mac129/eSim_Project_Files/MACProject.sch b/mac129/eSim_Project_Files/MACProject.sch new file mode 100644 index 0000000..5717f7b --- /dev/null +++ b/mac129/eSim_Project_Files/MACProject.sch @@ -0,0 +1,571 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital 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+$EndSCHEMATC diff --git a/ps2rx49/README.md.txt b/ps2rx49/README.md.txt new file mode 100644 index 0000000..07486c6 --- /dev/null +++ b/ps2rx49/README.md.txt @@ -0,0 +1,16 @@ +# ps2rx49 - PS/2 Keyboard Protocol Receiver + +## Description +A hardware receiver capable of safely crossing asynchronous clock boundaries to decode 11-bit PS/2 peripheral frames. The architecture features a 3-stage digital synchronizer to immunize the host system against external metastability and safely extract multi-cycle data payloads. + +## Block Diagram +Refer to the comprehensive project report for detailed schematics and block diagrams. + +## Pin Configuration +* **Inputs (4):** clk (1), rst (1), ps2_clk (1), ps2_data (1) +* **Outputs (9):** rx_data (8), rx_done (1) + +## Author & Contact +* **Name:** Hanzala Zafar +* **Institution:** Jamia Millia Islamia +* **GitHub:** [@zafarhanzala](https://github.com/zafarhanzala) \ No newline at end of file diff --git a/ps2rx49/Verilog_Files/ps2_rx.v b/ps2rx49/Verilog_Files/ps2_rx.v new file mode 100644 index 0000000..e917592 --- /dev/null +++ b/ps2rx49/Verilog_Files/ps2_rx.v @@ -0,0 +1,47 @@ +module ps2_rx ( + input clk, + input rst, + input ps2_clk, + input ps2_data, + output reg rx_done, + output reg [7:0] rx_data +); + + reg [3:0] bit_count; + reg [10:0] shift_reg; + reg [2:0] ps2_clk_sync; + + wire falling_edge; + + always @(posedge clk or posedge rst) begin + if (rst) begin + ps2_clk_sync <= 3'b111; + end else begin + ps2_clk_sync <= {ps2_clk_sync[1:0], ps2_clk}; + end + end + + assign falling_edge = (ps2_clk_sync[2:1] == 2'b10); + + always @(posedge clk or posedge rst) begin + if (rst) begin + bit_count <= 4'd0; + shift_reg <= 11'd0; + rx_done <= 1'b0; + rx_data <= 8'd0; + end else begin + rx_done <= 1'b0; + if (falling_edge) begin + shift_reg <= {ps2_data, shift_reg[10:1]}; + if (bit_count == 4'd10) begin + bit_count <= 4'd0; + rx_done <= 1'b1; + rx_data <= shift_reg[9:2]; + end else begin + bit_count <= bit_count + 1'b1; + end + end + end + end + +endmodule \ No newline at end of file diff --git a/ps2rx49/eSim_Project_Files/ps2_rx_sub.cir b/ps2rx49/eSim_Project_Files/ps2_rx_sub.cir new file mode 100644 index 0000000..d2ec5ee --- /dev/null +++ b/ps2rx49/eSim_Project_Files/ps2_rx_sub.cir @@ -0,0 +1,6 @@ +.title KiCad schematic +U2 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ ps2_rx +U3 Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ /rx_data7 /rx_data6 /rx_data5 /rx_data4 /rx_data3 /rx_data2 /rx_data1 /rx_data0 dac_bridge_8 +U4 Net-_U2-Pad5_ /rx_done dac_bridge_1 +U1 /clk /rst /ps2_clk /ps2_data Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ adc_bridge_4 +.end diff --git a/ps2rx49/eSim_Project_Files/ps2_rx_sub.cir.out b/ps2rx49/eSim_Project_Files/ps2_rx_sub.cir.out new file mode 100644 index 0000000..43f6593 --- /dev/null +++ b/ps2rx49/eSim_Project_Files/ps2_rx_sub.cir.out @@ -0,0 +1,27 @@ +.title kicad schematic + +* u2 net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ ps2_rx +* u3 net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ /rx_data7 /rx_data6 /rx_data5 /rx_data4 /rx_data3 /rx_data2 /rx_data1 /rx_data0 dac_bridge_8 +* u4 net-_u2-pad5_ /rx_done dac_bridge_1 +* u1 /clk /rst /ps2_clk /ps2_data net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ adc_bridge_4 +a1 [net-_u1-pad5_ ] [net-_u1-pad6_ ] [net-_u1-pad7_ ] [net-_u1-pad8_ ] [net-_u2-pad5_ ] [net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ ] u2 +a2 [net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ ] [/rx_data7 /rx_data6 /rx_data5 /rx_data4 /rx_data3 /rx_data2 /rx_data1 /rx_data0 ] u3 +a3 [net-_u2-pad5_ ] [/rx_done ] u4 +a4 [/clk /rst /ps2_clk /ps2_data ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u1 +* Schematic Name: ps2_rx, Ngspice Name: ps2_rx +.model u2 ps2_rx(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: dac_bridge_8, Ngspice Name: dac_bridge +.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_4, Ngspice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/ps2rx49/eSim_Project_Files/ps2_rx_sub.kicad_sch b/ps2rx49/eSim_Project_Files/ps2_rx_sub.kicad_sch new file mode 100644 index 0000000..ea7e7bb --- /dev/null +++ b/ps2rx49/eSim_Project_Files/ps2_rx_sub.kicad_sch @@ -0,0 +1,442 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid c6db77bb-b078-46a8-85b9-cf7c632317ec) + + (paper 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(unit 1) (value "ps2_rx") (footprint "") + ) + (path "/39acfd0e-8540-455c-9d39-9fd399c13d5c" + (reference "U3") (unit 1) (value "dac_bridge_8") (footprint "") + ) + (path "/2acb73fe-b16c-4bb7-ab70-7e3f31f88431" + (reference "U4") (unit 1) (value "dac_bridge_1") (footprint "") + ) + ) +) diff --git a/ps2rx49/eSim_Project_Files/ps2_rx_sub.sub b/ps2rx49/eSim_Project_Files/ps2_rx_sub.sub new file mode 100644 index 0000000..433966a --- /dev/null +++ b/ps2rx49/eSim_Project_Files/ps2_rx_sub.sub @@ -0,0 +1,19 @@ +* --- PS/2 Keyboard Receiver Subcircuit --- + +.subckt ps2_rx_sub clk rst ps2_clk ps2_data rx_done rx_data7 rx_data6 rx_data5 rx_data4 rx_data3 rx_data2 rx_data1 rx_data0 + +* --- ADC Bridges (Inputs) --- +A_adc_inputs [clk rst ps2_clk ps2_data] [d_clk d_rst d_ps2c d_ps2d] adc_1 + +* --- Verilog Digital Core --- +A_ps2_core [d_clk] [d_rst] [d_ps2c] [d_ps2d] [d_done] [d_d7 d_d6 d_d5 d_d4 d_d3 d_d2 d_d1 d_d0] ps2_rx + +* --- DAC Bridges (Outputs) --- +A_dac_outputs [d_done d_d7 d_d6 d_d5 d_d4 d_d3 d_d2 d_d1 d_d0] [rx_done rx_data7 rx_data6 rx_data5 rx_data4 rx_data3 rx_data2 rx_data1 rx_data0] dac_1 + +* --- Standard Bridge Models --- +.model adc_1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9) +.model dac_1 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9) +.model ps2_rx ps2_rx(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12) + +.ends ps2_rx_sub \ No newline at end of file diff --git a/ps2rx49/eSim_Project_Files/ps2_rx_tb.cir b/ps2rx49/eSim_Project_Files/ps2_rx_tb.cir new file mode 100644 index 0000000..db4d2e2 --- /dev/null +++ b/ps2rx49/eSim_Project_Files/ps2_rx_tb.cir @@ -0,0 +1,9 @@ +.title KiCad schematic +v3 /ps2_clk GND pulse +v2 /rst GND pulse +X1 /clk /rst /ps2_clk /ps2_data /rx_done rx_data7 rx_data6 rx_data5 rx_data4 rx_data3 rx_data2 rx_data1 /rx_data0 ps2_rx_sub +U1 /rx_done plot_v1 +U2 /rx_data0 plot_v1 +v4 /ps2_data GND pulse +v1 /clk GND pulse +.end diff --git a/ps2rx49/eSim_Project_Files/ps2_rx_tb.cir.out b/ps2rx49/eSim_Project_Files/ps2_rx_tb.cir.out new file mode 100644 index 0000000..cea0b1f --- /dev/null +++ b/ps2rx49/eSim_Project_Files/ps2_rx_tb.cir.out @@ -0,0 +1,21 @@ +.title kicad schematic + +.include ps2_rx_sub.sub +v3 /ps2_clk gnd pulse(5 0 5u 1n 1n 4900n 10u) +v2 /rst gnd pulse(5 0 2u 1n 1n 1000m 1000m) +x1 /clk /rst /ps2_clk /ps2_data /rx_done rx_data7 rx_data6 rx_data5 rx_data4 rx_data3 rx_data2 rx_data1 /rx_data0 ps2_rx_sub +* u1 /rx_done plot_v1 +* u2 /rx_data0 plot_v1 +v4 /ps2_data gnd pulse(0 5 0 1n 1n 13u 26u) +v1 /clk gnd pulse(0 5 0 1n 1n 490n 1u) +.tran 10e-09 150e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(/rx_done) +plot v(/rx_data0) +.endc +.end diff --git a/ps2rx49/eSim_Project_Files/ps2_rx_tb.kicad_sch b/ps2rx49/eSim_Project_Files/ps2_rx_tb.kicad_sch new file mode 100644 index 0000000..1cc3fd1 --- /dev/null +++ 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b/ps2rx49/eSim_Project_Files/ps2_rx_tb.proj new file mode 100644 index 0000000..53d3235 --- /dev/null +++ b/ps2rx49/eSim_Project_Files/ps2_rx_tb.proj @@ -0,0 +1 @@ +schematicFile ps2_rx_tb.kicad_sch diff --git a/seqdet31/README.md.txt b/seqdet31/README.md.txt new file mode 100644 index 0000000..bf6bbe2 --- /dev/null +++ b/seqdet31/README.md.txt @@ -0,0 +1,16 @@ +# seqdet31 - Overlapping Sequence Detector (1011) + +## Description +An Overlapping Sequence Detector targeting the specific 4-bit pattern "1011". It utilizes a resource-efficient Sliding-Window Pipeline shift register paired with a combinational match engine to monitor serial data streams without dropping consecutive overlapping bits. + +## Block Diagram +Refer to the comprehensive project report for detailed schematics and block diagrams. + +## Pin Configuration +* **Inputs (3):** clk (1), rst (1), data_in (1) +* **Outputs (1):** seq_found (1) + +## Author & Contact +* **Name:** Hanzala Zafar +* **Institution:** Jamia Millia Islamia +* **GitHub:** [@zafarhanzala](https://github.com/zafarhanzala) \ No newline at end of file diff --git a/seqdet31/Verilog_Files/seq_detector_1011.v b/seqdet31/Verilog_Files/seq_detector_1011.v new file mode 100644 index 0000000..ec391f4 --- /dev/null +++ b/seqdet31/Verilog_Files/seq_detector_1011.v @@ -0,0 +1,25 @@ +module seq_detector_1011 ( + input wire clk, + input wire reset, + input wire data_in, + output reg detected +); + + reg [3:0] shift_reg; + + always @(posedge clk or posedge reset) begin + if (reset) begin + shift_reg <= 4'b0000; + detected <= 1'b0; + end else begin + // Shift the pipeline left and push the new data_in bit to the right + shift_reg <= {shift_reg[2:0], data_in}; + + // Constantly monitor the pipeline. If it matches 1011, trigger the output! + if ({shift_reg[2:0], data_in} == 4'b1011) + detected <= 1'b1; + else + detected <= 1'b0; + end + end +endmodule \ No newline at end of file diff --git a/seqdet31/eSim_Project_Files/OSD2.cir b/seqdet31/eSim_Project_Files/OSD2.cir new file mode 100644 index 0000000..d8c255e --- /dev/null +++ b/seqdet31/eSim_Project_Files/OSD2.cir @@ -0,0 +1,7 @@ +.title KiCad schematic +U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad4_ seq_detector_1011 +U5 Net-_U4-Pad4_ /detect_out dac_bridge_1 +U1 /clk_in Net-_U1-Pad2_ adc_bridge_1 +U2 /reset_in Net-_U2-Pad2_ adc_bridge_1 +U3 /data_in Net-_U3-Pad2_ adc_bridge_1 +.end diff --git a/seqdet31/eSim_Project_Files/OSD2.cir.out b/seqdet31/eSim_Project_Files/OSD2.cir.out new file mode 100644 index 0000000..b2845ee --- /dev/null +++ b/seqdet31/eSim_Project_Files/OSD2.cir.out @@ -0,0 +1,31 @@ +.title kicad schematic + +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad4_ seq_detector_1011 +* u5 net-_u4-pad4_ /detect_out dac_bridge_1 +* u1 /clk_in net-_u1-pad2_ adc_bridge_1 +* u2 /reset_in net-_u2-pad2_ adc_bridge_1 +* u3 /data_in net-_u3-pad2_ adc_bridge_1 +a1 [net-_u1-pad2_ ] [net-_u2-pad2_ ] [net-_u3-pad2_ ] [net-_u4-pad4_ ] u4 +a2 [net-_u4-pad4_ ] [/detect_out ] u5 +a3 [/clk_in ] [net-_u1-pad2_ ] u1 +a4 [/reset_in ] [net-_u2-pad2_ ] u2 +a5 [/data_in ] [net-_u3-pad2_ ] u3 +* Schematic Name: seq_detector_1011, Ngspice Name: seq_detector_1011 +.model u4 seq_detector_1011(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/seqdet31/eSim_Project_Files/OSD2.kicad_sch b/seqdet31/eSim_Project_Files/OSD2.kicad_sch new file mode 100644 index 0000000..17a9258 --- /dev/null +++ b/seqdet31/eSim_Project_Files/OSD2.kicad_sch @@ -0,0 +1,253 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 92613011-94c2-431b-8b66-89c120fcccc7) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Hybrid:adc_bridge_1" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "adc_bridge_1" (id 1) (at 0 3.81 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font 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fall_delay=1.0e-9 input_load=1.0e-12) + +.ends osd2 \ No newline at end of file diff --git a/seqdet31/eSim_Project_Files/Sequence_dettb.cir b/seqdet31/eSim_Project_Files/Sequence_dettb.cir new file mode 100644 index 0000000..27bf6b5 --- /dev/null +++ b/seqdet31/eSim_Project_Files/Sequence_dettb.cir @@ -0,0 +1,6 @@ +.title KiCad schematic +v3 data GND pulse +X1 clk reset data detect OSD2 +v2 reset GND pulse +v1 clk GND pulse +.end diff --git a/seqdet31/eSim_Project_Files/Sequence_dettb.cir.out b/seqdet31/eSim_Project_Files/Sequence_dettb.cir.out new file mode 100644 index 0000000..f749906 --- /dev/null +++ b/seqdet31/eSim_Project_Files/Sequence_dettb.cir.out @@ -0,0 +1,16 @@ +.title kicad schematic + +.include OSD2.sub +v3 data gnd pulse(0 5 5m 1u 1u 15m 30m) +x1 clk reset data detect OSD2 +v2 reset gnd pulse(5 0 2m 1u 1u 1000m 1000m) +v1 clk gnd pulse(0 5 0 1u 1u 5m 10m) +.tran 100e-06 60e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/seqdet31/eSim_Project_Files/Sequence_dettb.kicad_sch b/seqdet31/eSim_Project_Files/Sequence_dettb.kicad_sch new file mode 100644 index 0000000..b984b9f --- /dev/null +++ b/seqdet31/eSim_Project_Files/Sequence_dettb.kicad_sch @@ -0,0 +1,335 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 9dfd0065-2162-489e-97cf-e1172d42d59b) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Power:eSim_GND" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes) + (property "Reference" "#PWR" (id 0) (at 0 -6.35 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Value" "eSim_GND" (id 1) (at 0 -3.81 0) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "eSim_GND_0_1" + (polyline + (pts + (xy 0 0) + (xy 0 -1.27) + (xy 1.27 -1.27) + (xy 0 -2.54) + (xy -1.27 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0000000..638083c --- /dev/null +++ b/seqdet31/eSim_Project_Files/Sequence_dettb.proj @@ -0,0 +1 @@ +schematicFile Sequence_dettb.kicad_sch diff --git a/vendfsm517/README.md.txt b/vendfsm517/README.md.txt new file mode 100644 index 0000000..676193b --- /dev/null +++ b/vendfsm517/README.md.txt @@ -0,0 +1,16 @@ +# vendfsm517 - Vending Machine Controller FSM + +## Description +A robust 3-State Vending Machine Finite State Machine (FSM) engineered with internal digital edge-detectors. The core processes user transactions, accumulates funds, dispenses products, and calculates change while being mathematically immunized against the physical reality of analog mechanical button bouncing. + +## Block Diagram +Refer to the comprehensive project report for detailed schematics and block diagrams. + +## Pin Configuration +* **Inputs (5):** clk (1), rst (1), coin_50 (1), coin_100 (1), buy (1) +* **Outputs (17):** dispense (1), change (8), balance (8) + +## Author & Contact +* **Name:** Hanzala Zafar +* **Institution:** Jamia Millia Islamia +* **GitHub:** [@zafarhanzala](https://github.com/zafarhanzala) \ No newline at end of file diff --git a/vendfsm517/Verilog_Files/vending_fsm.v b/vendfsm517/Verilog_Files/vending_fsm.v new file mode 100644 index 0000000..a2017ef --- /dev/null +++ b/vendfsm517/Verilog_Files/vending_fsm.v @@ -0,0 +1,78 @@ +module vending_fsm ( + input clk, + input rst, + input coin_5, + input coin_10, + input buy, + output reg dispense, + output reg [7:0] change, + output reg [7:0] balance +); + + parameter PRICE = 8'd15; + + // FSM State Encoding + parameter IDLE = 2'd0; + parameter VEND = 2'd1; + parameter RETURN = 2'd2; + + reg [1:0] state; + + // Edge Detectors (Crucial for mixed-signal Vpulse compatibility) + reg c5_d, c10_d, buy_d; + wire c5_pulse = coin_5 & ~c5_d; + wire c10_pulse = coin_10 & ~c10_d; + wire buy_pulse = buy & ~buy_d; + + always @(posedge clk or posedge rst) begin + if (rst) begin + c5_d <= 1'b0; + c10_d <= 1'b0; + buy_d <= 1'b0; + state <= IDLE; + balance <= 8'd0; + dispense <= 1'b0; + change <= 8'd0; + end else begin + // 1. Update delayed signals for edge detection + c5_d <= coin_5; + c10_d <= coin_10; + buy_d <= buy; + + // 2. Default outputs (Stops them from latching high permanently) + dispense <= 1'b0; + + // 3. FSM State Transitions + case (state) + IDLE: begin + change <= 8'd0; // Clear change display + + if (c5_pulse) begin + balance <= balance + 8'd5; + end else if (c10_pulse) begin + balance <= balance + 8'd10; + end else if (buy_pulse) begin + if (balance >= PRICE) begin + state <= VEND; + end + end + end + + VEND: begin + dispense <= 1'b1; // Trigger the drop mechanism + balance <= balance - PRICE; // Deduct the cost + state <= RETURN; + end + + RETURN: begin + change <= balance; // Spit out the remaining balance + balance <= 8'd0; // Reset internal tracker + state <= IDLE; + end + + default: state <= IDLE; + endcase + end + end + +endmodule \ No newline at end of file diff --git a/vendfsm517/eSim_Project_Files/vending_fsm_sb.cir b/vendfsm517/eSim_Project_Files/vending_fsm_sb.cir new file mode 100644 index 0000000..636bedb --- /dev/null +++ b/vendfsm517/eSim_Project_Files/vending_fsm_sb.cir @@ -0,0 +1,7 @@ +.title KiCad schematic +U3 Net-_U2-Pad22_ /balance0 dac_bridge_1 +U5 Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ /dispense /change7 /change6 /change5 /change4 /change3 /change2 /change1 dac_bridge_8 +U4 Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U2-Pad17_ Net-_U2-Pad18_ Net-_U2-Pad19_ Net-_U2-Pad20_ Net-_U2-Pad21_ /change0 /balance7 /balance6 /balance5 /balance4 /balance3 /balance2 /balance1 dac_bridge_8 +U2 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U2-Pad17_ Net-_U2-Pad18_ Net-_U2-Pad19_ Net-_U2-Pad20_ Net-_U2-Pad21_ Net-_U2-Pad22_ vending_fsm +U1 /clk /rst /coin_50 /coin_100 /buy Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ adc_bridge_5 +.end diff --git a/vendfsm517/eSim_Project_Files/vending_fsm_sb.cir.out b/vendfsm517/eSim_Project_Files/vending_fsm_sb.cir.out new file mode 100644 index 0000000..750754e --- /dev/null +++ b/vendfsm517/eSim_Project_Files/vending_fsm_sb.cir.out @@ -0,0 +1,31 @@ +.title kicad schematic + +* u3 net-_u2-pad22_ /balance0 dac_bridge_1 +* u5 net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ /dispense /change7 /change6 /change5 /change4 /change3 /change2 /change1 dac_bridge_8 +* u4 net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_ net-_u2-pad21_ /change0 /balance7 /balance6 /balance5 /balance4 /balance3 /balance2 /balance1 dac_bridge_8 +* u2 net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_ net-_u2-pad21_ net-_u2-pad22_ vending_fsm +* u1 /clk /rst /coin_50 /coin_100 /buy net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ adc_bridge_5 +a1 [net-_u2-pad22_ ] [/balance0 ] u3 +a2 [net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ ] [/dispense /change7 /change6 /change5 /change4 /change3 /change2 /change1 ] u5 +a3 [net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_ net-_u2-pad21_ ] [/change0 /balance7 /balance6 /balance5 /balance4 /balance3 /balance2 /balance1 ] u4 +a4 [net-_u1-pad6_ ] [net-_u1-pad7_ ] [net-_u1-pad8_ ] [net-_u1-pad9_ ] [net-_u1-pad10_ ] [net-_u2-pad6_ ] [net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ ] [net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_ net-_u2-pad21_ net-_u2-pad22_ ] u2 +a5 [/clk /rst /coin_50 /coin_100 /buy ] [net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ ] u1 +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_8, Ngspice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_8, Ngspice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: vending_fsm, Ngspice Name: vending_fsm +.model u2 vending_fsm(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: adc_bridge_5, Ngspice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt 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a/vendfsm517/eSim_Project_Files/vending_fsm_sb.sub b/vendfsm517/eSim_Project_Files/vending_fsm_sb.sub new file mode 100644 index 0000000..5128517 --- /dev/null +++ b/vendfsm517/eSim_Project_Files/vending_fsm_sb.sub @@ -0,0 +1,19 @@ +* --- Vending Machine FSM Subcircuit --- + +.subckt vending_fsm_sb clk rst coin_50 coin_100 buy dispense change7 change6 change5 change4 change3 change2 change1 change0 balance7 balance6 balance5 balance4 balance3 balance2 balance1 balance0 + +* --- ADC Bridge (Inputs) --- +A_adc_inputs [clk rst coin_50 coin_100 buy] [d_clk d_rst d_c50 d_c100 d_buy] adc_1 + +* --- Verilog Digital Core --- +A_fsm_core [d_clk] [d_rst] [d_c50] [d_c100] [d_buy] [d_dispense] [d_ch7 d_ch6 d_ch5 d_ch4 d_ch3 d_ch2 d_ch1 d_ch0] [d_bal7 d_bal6 d_bal5 d_bal4 d_bal3 d_bal2 d_bal1 d_bal0] vending_fsm + +* --- DAC Bridge (Outputs) --- +A_dac_outputs [d_dispense d_ch7 d_ch6 d_ch5 d_ch4 d_ch3 d_ch2 d_ch1 d_ch0 d_bal7 d_bal6 d_bal5 d_bal4 d_bal3 d_bal2 d_bal1 d_bal0] [dispense change7 change6 change5 change4 change3 change2 change1 change0 balance7 balance6 balance5 balance4 balance3 balance2 balance1 balance0] dac_1 + +* --- Standard Bridge Models --- +.model adc_1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9) +.model dac_1 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9) +.model vending_fsm vending_fsm(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12) + +.ends vending_fsm_sb \ No newline at end of file diff --git a/vendfsm517/eSim_Project_Files/vending_fsm_tb.cir b/vendfsm517/eSim_Project_Files/vending_fsm_tb.cir new file mode 100644 index 0000000..c3de26d --- /dev/null +++ b/vendfsm517/eSim_Project_Files/vending_fsm_tb.cir @@ -0,0 +1,13 @@ +.title KiCad schematic +v3 /coin_50 GND pulse +v4 /coin_100 GND pulse +v1 /clk GND pulse +v2 /rst GND pulse +v5 /buy GND pulse +X1 /clk /rst /coin_50 /coin_100 /buy /deispense change7 chnage6 change5 change4 change3 change2 /change1 /change0 balance7 balance6 balance5 balance4 balance3 balance2 /balance1 /balance0 vending_fsm_sb +U1 /deispense plot_v1 +U4 /change0 plot_v1 +U2 /change1 plot_v1 +U5 /balance0 plot_v1 +U3 /balance1 plot_v1 +.end diff --git a/vendfsm517/eSim_Project_Files/vending_fsm_tb.cir.out b/vendfsm517/eSim_Project_Files/vending_fsm_tb.cir.out new file mode 100644 index 0000000..36aef99 --- /dev/null +++ b/vendfsm517/eSim_Project_Files/vending_fsm_tb.cir.out @@ -0,0 +1,28 @@ +.title kicad schematic + +.include vending_fsm_sb.sub +v3 /coin_50 gnd pulse(0 5 5u 1n 1n 2u 100m) +v4 /coin_100 gnd pulse(0 5 10u 1n 1n 2u 100m) +v1 /clk gnd pulse(0 5 0 1n 1n 490n 1u) +v2 /rst gnd pulse(5 0 2u 1n 1n 100m 100m) +v5 /buy gnd pulse(0 5 15u 1n 1n 2u 100m) +x1 /clk /rst /coin_50 /coin_100 /buy /deispense change7 chnage6 change5 change4 change3 change2 /change1 /change0 balance7 balance6 balance5 balance4 balance3 balance2 /balance1 /balance0 vending_fsm_sb +* u1 /deispense plot_v1 +* u4 /change0 plot_v1 +* u2 /change1 plot_v1 +* u5 /balance0 plot_v1 +* u3 /balance1 plot_v1 +.tran 10e-09 25e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(/deispense) +plot v(/change0) +plot v(/change1) +plot v(/balance0) +plot v(/balance1) +.endc +.end diff --git a/vendfsm517/eSim_Project_Files/vending_fsm_tb.kicad_sch b/vendfsm517/eSim_Project_Files/vending_fsm_tb.kicad_sch new file mode 100644 index 0000000..0eb772d --- /dev/null +++ b/vendfsm517/eSim_Project_Files/vending_fsm_tb.kicad_sch @@ -0,0 +1,771 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid c0b73db3-d5be-4082-9947-c36d05ca81e4) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Plot:plot_v1" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 12.7 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "plot_v1" (id 1) (at 5.08 8.89 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 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resolution display at a 60Hz refresh rate. It utilizes nested horizontal and vertical counters to synchronize active video areas and blanking intervals. + +## Block Diagram +Refer to the comprehensive project report for detailed schematics and block diagrams. + +## Pin Configuration +* **Inputs (2):** clk (1), reset (1) +* **Outputs (23):** h_sync (1), v_sync (1), video_on (1), pixel_x (10), pixel_y (10) + +## Author & Contact +* **Name:** Hanzala Zafar +* **Institution:** Jamia Millia Islamia +* **GitHub:** [@zafarhanzala](https://github.com/zafarhanzala) \ No newline at end of file diff --git a/vga223/Verilog_Files/vga_timing_gen.v b/vga223/Verilog_Files/vga_timing_gen.v new file mode 100644 index 0000000..20993b9 --- /dev/null +++ b/vga223/Verilog_Files/vga_timing_gen.v @@ -0,0 +1,63 @@ +module vga_timing_gen ( + input wire clk, // 25 MHz Pixel Clock + input wire rst, // Asynchronous reset + output reg hsync, // Horizontal sync pulse + output reg vsync, // Vertical sync pulse + output wire video_on,// High when in the 640x480 visible area + output reg [9:0] x_pos, // Current pixel column (0 to 799) + output reg [9:0] y_pos // Current pixel row (0 to 524) +); + + // --- VGA 640x480 @ 60Hz Industry Standard Parameters --- + parameter H_DISPLAY = 640; + parameter H_FRONT = 16; + parameter H_SYNC = 96; + parameter H_BACK = 48; + parameter H_TOTAL = 800; // 640 + 16 + 96 + 48 + + parameter V_DISPLAY = 480; + parameter V_FRONT = 10; + parameter V_SYNC = 2; + parameter V_BACK = 33; + parameter V_TOTAL = 525; // 480 + 10 + 2 + 33 + + // --- Horizontal Pixel Counter --- + always @(posedge clk or posedge rst) begin + if (rst) + x_pos <= 10'd0; + else if (x_pos == H_TOTAL - 1) + x_pos <= 10'd0; + else + x_pos <= x_pos + 10'd1; + end + + // --- Vertical Line Counter --- + // Only increments when the horizontal counter finishes a full row + always @(posedge clk or posedge rst) begin + if (rst) + y_pos <= 10'd0; + else if (x_pos == H_TOTAL - 1) begin + if (y_pos == V_TOTAL - 1) + y_pos <= 10'd0; + else + y_pos <= y_pos + 10'd1; + end + end + + // --- Sync Pulse Generation --- + // Standard VGA requires active-low sync pulses + always @(posedge clk or posedge rst) begin + if (rst) begin + hsync <= 1'b1; + vsync <= 1'b1; + end else begin + hsync <= ~((x_pos >= (H_DISPLAY + H_FRONT)) && (x_pos < (H_DISPLAY + H_FRONT + H_SYNC))); + vsync <= ~((y_pos >= (V_DISPLAY + V_FRONT)) && (y_pos < (V_DISPLAY + V_FRONT + V_SYNC))); + end + end + + // --- Video On Flag --- + // True only when the counters are inside the visible 640x480 grid + assign video_on = (x_pos < H_DISPLAY) && (y_pos < V_DISPLAY); + +endmodule \ No newline at end of file diff --git a/vga223/eSim_Project_Files/VGA_testbench.cir b/vga223/eSim_Project_Files/VGA_testbench.cir new file mode 100644 index 0000000..7ea59a3 --- /dev/null +++ b/vga223/eSim_Project_Files/VGA_testbench.cir @@ -0,0 +1,8 @@ +.title KiCad schematic +v1 Net-_X1-Pad1_ GND pulse +v2 Net-_X1-Pad2_ GND pulse +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ /hsync_plot /vsync_plot /video x_pos9 x_pos8 x_pos7 x_pos6 x_pos5 x_pos4 x_pos3 x_pos2 x_pos1 x_pos0 y_pos9 y_pos8 y_pos7 y_pos6 y_pos5 y_pos4 y_pos3 y_pos2 y_pos1 y_pos0 vga +U3 /video plot_v1 +U2 /vsync_plot plot_v1 +U1 /hsync_plot plot_v1 +.end diff --git a/vga223/eSim_Project_Files/VGA_testbench.cir.out b/vga223/eSim_Project_Files/VGA_testbench.cir.out new file mode 100644 index 0000000..37235bb --- /dev/null +++ b/vga223/eSim_Project_Files/VGA_testbench.cir.out @@ -0,0 +1,21 @@ +.title kicad schematic + +.include vga.sub +v1 net-_x1-pad1_ gnd pulse(0 5 0 1n 1n 19n 40n) +v2 net-_x1-pad2_ gnd pulse(5 0 100n 1n 1n 1000m 1000m) +x1 net-_x1-pad1_ net-_x1-pad2_ /hsync_plot /vsync_plot /video x_pos9 x_pos8 x_pos7 x_pos6 x_pos5 x_pos4 x_pos3 x_pos2 x_pos1 x_pos0 y_pos9 y_pos8 y_pos7 y_pos6 y_pos5 y_pos4 y_pos3 y_pos2 y_pos1 y_pos0 vga +* u3 /video plot_v1 +* u2 /vsync_plot plot_v1 +* u1 /hsync_plot plot_v1 +.tran 10e-09 100e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > 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b/vga223/eSim_Project_Files/VGA_testbench.proj new file mode 100644 index 0000000..a53aba8 --- /dev/null +++ b/vga223/eSim_Project_Files/VGA_testbench.proj @@ -0,0 +1 @@ +schematicFile VGA_testbench.kicad_sch diff --git a/vga223/eSim_Project_Files/vga.cir b/vga223/eSim_Project_Files/vga.cir new file mode 100644 index 0000000..fcd59cb --- /dev/null +++ b/vga223/eSim_Project_Files/vga.cir @@ -0,0 +1,11 @@ +.title KiCad schematic +U1 /clk Net-_U1-Pad2_ adc_bridge_1 +U2 /rst Net-_U2-Pad2_ adc_bridge_1 +U3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U3-Pad9_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U3-Pad12_ Net-_U3-Pad13_ Net-_U3-Pad14_ Net-_U3-Pad15_ Net-_U3-Pad16_ Net-_U3-Pad17_ Net-_U3-Pad18_ Net-_U3-Pad19_ Net-_U3-Pad20_ Net-_U3-Pad21_ Net-_U3-Pad22_ Net-_U3-Pad23_ Net-_U3-Pad24_ Net-_U3-Pad25_ vga_timing_gen +U6 Net-_U3-Pad18_ Net-_U3-Pad19_ Net-_U3-Pad20_ Net-_U3-Pad21_ Net-_U3-Pad22_ Net-_U3-Pad23_ Net-_U3-Pad24_ Net-_U3-Pad25_ /y_pos7 /y_pos6 /y_pos5 /y_pos4 /y_pos3 /y_pos2 /y_pos1 /y_pos0 dac_bridge_8 +U4 Net-_U3-Pad3_ /hsync dac_bridge_1 +U7 Net-_U3-Pad4_ /vsync dac_bridge_1 +U8 Net-_U3-Pad5_ /video_on dac_bridge_1 +U9 Net-_U3-Pad14_ Net-_U3-Pad15_ Net-_U3-Pad16_ Net-_U3-Pad17_ /x_pos1 /x_pos0 /y_pos9 /y_pos8 dac_bridge_4 +U5 Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U3-Pad9_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U3-Pad12_ Net-_U3-Pad13_ /x_pos9 /x_pos8 /x_pos7 /x_pos6 /x_pos5 /x_pos4 /x_pos3 /x_pos2 dac_bridge_8 +.end diff --git a/vga223/eSim_Project_Files/vga.cir.out b/vga223/eSim_Project_Files/vga.cir.out new file mode 100644 index 0000000..24087fa --- /dev/null +++ b/vga223/eSim_Project_Files/vga.cir.out @@ -0,0 +1,47 @@ +.title kicad schematic + +* u1 /clk net-_u1-pad2_ adc_bridge_1 +* u2 /rst net-_u2-pad2_ adc_bridge_1 +* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ net-_u3-pad17_ net-_u3-pad18_ net-_u3-pad19_ net-_u3-pad20_ net-_u3-pad21_ net-_u3-pad22_ net-_u3-pad23_ net-_u3-pad24_ net-_u3-pad25_ vga_timing_gen +* u6 net-_u3-pad18_ net-_u3-pad19_ net-_u3-pad20_ net-_u3-pad21_ net-_u3-pad22_ net-_u3-pad23_ net-_u3-pad24_ net-_u3-pad25_ /y_pos7 /y_pos6 /y_pos5 /y_pos4 /y_pos3 /y_pos2 /y_pos1 /y_pos0 dac_bridge_8 +* u4 net-_u3-pad3_ /hsync dac_bridge_1 +* u7 net-_u3-pad4_ /vsync dac_bridge_1 +* u8 net-_u3-pad5_ /video_on dac_bridge_1 +* u9 net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ net-_u3-pad17_ /x_pos1 /x_pos0 /y_pos9 /y_pos8 dac_bridge_4 +* u5 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ /x_pos9 /x_pos8 /x_pos7 /x_pos6 /x_pos5 /x_pos4 /x_pos3 /x_pos2 dac_bridge_8 +a1 [/clk ] [net-_u1-pad2_ ] u1 +a2 [/rst ] [net-_u2-pad2_ ] u2 +a3 [net-_u1-pad2_ ] [net-_u2-pad2_ ] [net-_u3-pad3_ ] [net-_u3-pad4_ ] [net-_u3-pad5_ ] [net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_u3-pad14_ net-_u3-pad15_ ] [net-_u3-pad16_ net-_u3-pad17_ net-_u3-pad18_ net-_u3-pad19_ net-_u3-pad20_ net-_u3-pad21_ net-_u3-pad22_ net-_u3-pad23_ net-_u3-pad24_ net-_u3-pad25_ ] u3 +a4 [net-_u3-pad18_ net-_u3-pad19_ net-_u3-pad20_ net-_u3-pad21_ net-_u3-pad22_ net-_u3-pad23_ net-_u3-pad24_ net-_u3-pad25_ ] [/y_pos7 /y_pos6 /y_pos5 /y_pos4 /y_pos3 /y_pos2 /y_pos1 /y_pos0 ] u6 +a5 [net-_u3-pad3_ ] [/hsync ] u4 +a6 [net-_u3-pad4_ ] [/vsync ] u7 +a7 [net-_u3-pad5_ ] [/video_on ] u8 +a8 [net-_u3-pad14_ net-_u3-pad15_ net-_u3-pad16_ net-_u3-pad17_ ] [/x_pos1 /x_pos0 /y_pos9 /y_pos8 ] u9 +a9 [net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ ] [/x_pos9 /x_pos8 /x_pos7 /x_pos6 /x_pos5 /x_pos4 /x_pos3 /x_pos2 ] u5 +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: vga_timing_gen, Ngspice Name: vga_timing_gen +.model u3 vga_timing_gen(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: dac_bridge_8, Ngspice Name: dac_bridge +.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u7 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_4, Ngspice Name: dac_bridge +.model u9 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_8, Ngspice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/vga223/eSim_Project_Files/vga.kicad_sch b/vga223/eSim_Project_Files/vga.kicad_sch new file mode 100644 index 0000000..8fa987a --- /dev/null +++ b/vga223/eSim_Project_Files/vga.kicad_sch @@ -0,0 +1,784 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 743ad4ed-bd40-4f1b-812d-4f9000b6a074) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Hybrid:adc_bridge_1" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) 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"") + ) + (path "/8d7113e0-5ea8-4d81-91d8-e653a3447166" + (reference "U5") (unit 1) (value "dac_bridge_8") (footprint "") + ) + (path "/c022c858-4d6c-476f-a089-ee7628dff1a6" + (reference "U6") (unit 1) (value "dac_bridge_8") (footprint "") + ) + (path "/e787adbf-e90d-414f-b193-4202e3ccd7d5" + (reference "U7") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/49a19e4b-db4b-4a59-8cf1-6783cb946610" + (reference "U8") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/03a51711-a1c4-4006-99ba-c1613ced8c59" + (reference "U9") (unit 1) (value "dac_bridge_4") (footprint "") + ) + ) +) diff --git a/vga223/eSim_Project_Files/vga.sub b/vga223/eSim_Project_Files/vga.sub new file mode 100644 index 0000000..fc5ad99 --- /dev/null +++ b/vga223/eSim_Project_Files/vga.sub @@ -0,0 +1,44 @@ +.subckt vga clk rst hsync vsync video_on x_pos9 x_pos8 x_pos7 x_pos6 x_pos5 x_pos4 x_pos3 x_pos2 x_pos1 x_pos0 y_pos9 y_pos8 y_pos7 y_pos6 y_pos5 y_pos4 y_pos3 y_pos2 y_pos1 y_pos0 + +* --- ADC Bridges (Inputs) --- +A_adc_clk [clk] [d_clk] adc_1 +A_adc_rst [rst] [d_rst] adc_1 + +* --- Verilog Core --- +A_vga [d_clk] [d_rst] [d_hsync] [d_vsync] [d_vidon] [d_x9 d_x8 d_x7 d_x6 d_x5 d_x4 d_x3 d_x2 d_x1 d_x0] [d_y9 d_y8 d_y7 d_y6 d_y5 d_y4 d_y3 d_y2 d_y1 d_y0] vga_timing_gen + +* --- DAC Bridges (Control Signals) --- +A_dac_hsync [d_hsync] [hsync] dac_1 +A_dac_vsync [d_vsync] [vsync] dac_1 +A_dac_vidon [d_vidon] [video_on] dac_1 + +* --- DAC Bridges (10-Bit X Position Bus) --- +A_dac_x9 [d_x9] [x_pos9] dac_1 +A_dac_x8 [d_x8] [x_pos8] dac_1 +A_dac_x7 [d_x7] [x_pos7] dac_1 +A_dac_x6 [d_x6] [x_pos6] dac_1 +A_dac_x5 [d_x5] [x_pos5] dac_1 +A_dac_x4 [d_x4] [x_pos4] dac_1 +A_dac_x3 [d_x3] [x_pos3] dac_1 +A_dac_x2 [d_x2] [x_pos2] dac_1 +A_dac_x1 [d_x1] [x_pos1] dac_1 +A_dac_x0 [d_x0] [x_pos0] dac_1 + +* --- DAC Bridges (10-Bit Y Position Bus) --- +A_dac_y9 [d_y9] [y_pos9] dac_1 +A_dac_y8 [d_y8] [y_pos8] dac_1 +A_dac_y7 [d_y7] [y_pos7] dac_1 +A_dac_y6 [d_y6] [y_pos6] dac_1 +A_dac_y5 [d_y5] [y_pos5] dac_1 +A_dac_y4 [d_y4] [y_pos4] dac_1 +A_dac_y3 [d_y3] [y_pos3] dac_1 +A_dac_y2 [d_y2] [y_pos2] dac_1 +A_dac_y1 [d_y1] [y_pos1] dac_1 +A_dac_y0 [d_y0] [y_pos0] dac_1 + +* --- Models --- +.model adc_1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9) +.model dac_1 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9) +.model vga_timing_gen vga_timing_gen(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12) + +.ends vga \ No newline at end of file diff --git a/vga223/eSim_Project_Files/vga_custom.kicad_sym b/vga223/eSim_Project_Files/vga_custom.kicad_sym new file mode 100644 index 0000000..583f729 --- /dev/null +++ b/vga223/eSim_Project_Files/vga_custom.kicad_sym @@ -0,0 +1,124 @@ +(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor) + (symbol "vga" (in_bom yes) (on_board yes) + (property "Reference" "X" (id 0) (at 3.81 -25.4 0) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "vga" 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